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Message-ID: <20190813101005.GA10751@bogon.m.sigxcpu.org>
Date: Tue, 13 Aug 2019 12:10:05 +0200
From: Guido Günther <agx@...xcpu.org>
To: Rob Herring <robh+dt@...nel.org>
Cc: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
Mark Rutland <mark.rutland@....com>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Andrzej Hajda <a.hajda@...sung.com>,
Neil Armstrong <narmstrong@...libre.com>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Lee Jones <lee.jones@...aro.org>,
dri-devel <dri-devel@...ts.freedesktop.org>,
devicetree@...r.kernel.org,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Robert Chiras <robert.chiras@....com>,
Sam Ravnborg <sam@...nborg.org>
Subject: Re: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL
mipi dsi host controller
Hi Rob,
thanks for having a look!
On Fri, Aug 09, 2019 at 02:41:03PM -0600, Rob Herring wrote:
> On Fri, Aug 9, 2019 at 10:24 AM Guido Günther <agx@...xcpu.org> wrote:
> >
> > The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
> >
> > Signed-off-by: Guido Günther <agx@...xcpu.org>
> > ---
> > .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++
> > 1 file changed, 155 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> > new file mode 100644
> > index 000000000000..5ed8bc4a4d18
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> > @@ -0,0 +1,155 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Northwest Logic MIPI-DSI on imx SoCs
> > +
> > +maintainers:
> > + - Guido Gúnther <agx@...xcpu.org>
> > + - Robert Chiras <robert.chiras@....com>
> > +
> > +description: |
> > + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
> > + the SOCs NWL MIPI-DSI host controller.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: fsl,imx8mq-nwl-dsi
>
> Don't need oneOf nor items here for a single possible value:
I wanted to prepare for adding other SoCs so there's less diff noise
(other imx8 SoCs will be rather simple) but let's go with 'const' for
now then.
> compatible:
> const: fsl,imx8mq-nwl-dsi
>
> Or go ahead and add other compatibles because the 'if' below seems to
> indicate you'll have more.
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: DSI core clock
> > + - description: RX_ESC clock (used in escape mode)
> > + - description: TX_ESC clock (used in escape mode)
> > + - description: PHY_REF clock
> > +
> > + clock-names:
> > + items:
> > + - const: core
> > + - const: rx_esc
> > + - const: tx_esc
> > + - const: phy_ref
> > +
> > + phys:
> > + maxItems: 1
> > + description:
> > + A phandle to the phy module representing the DPHY
> > +
> > + phy-names:
> > + items:
> > + - const: dphy
> > +
> > + power-domains:
> > + maxItems: 1
> > + description:
> > + A phandle to the power domain
> > +
> > + resets:
> > + maxItems: 4
> > + description:
> > + A phandle to the reset controller
>
> Sounds like 4 phandles... This should look similar to 'clocks'.
Added them individually, will be soc specific too later on.
>
> > +
> > + reset-names:
> > + items:
> > + - const: byte
> > + - const: dpi
> > + - const: esc
> > + - const: pclk
> > +
> > + mux-sel:
>
> Needs a vendor prefix and will need a $ref to the type.
Made that fsl,mux-sel. This require me to add '$ref:
/schemas/types.yaml#definitions/phandle' as well which
I hope is correct.
> > + maxItems: 1
> > + description:
> > + A phandle to the MUX register set
> > +
> > + port:
> > + type: object
> > + description:
> > + A input put or output port node.
> > +
> > + ports:
> > + type: object
> > + description:
> > + A node containing DSI input & output port nodes with endpoint
> > + definitions as documented in
> > + Documentation/devicetree/bindings/graph.txt.
>
> You need to define what port@0 and port@1 are.
Added.
>
> > +
> > +patternProperties:
> > + "^panel@[0-9]+$": true
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx8mq-nwl-dsi
>
> This conditional isn't needed until you have more than one compatible.
Again intended for other upcoming SoCs but dropped for now.
> > + required:
> > + - resets
> > + - reset-names
> > + - mux-sel
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - phys
> > + - phy-names
>
> ports should be required.
Added.
> > +
> > +examples:
> > + - |
> > +
> > + mipi_dsi: mipi_dsi@...00000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "fsl,imx8mq-nwl-dsi";
> > + reg = <0x30A00000 0x300>;
> > + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>;
> > + clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
> > + interrupts = <0 34 4>;
> > + power-domains = <&pgc_mipi>;
> > + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>;
> > + reset-names = "byte", "dpi", "esc", "pclk";
> > + mux-sel = <&iomuxc_gpr>;
> > + phys = <&dphy>;
> > + phy-names = "dphy";
> > +
> > + panel@0 {
> > + compatible = "...";
>
> Needs to be a valid compatible. Also need 'reg' here or drop the
> unit-address.
Fixed.
>
>
> > + port@0 {
> > + panel_in: endpoint {
> > + remote-endpoint = <&mipi_dsi_out>;
> > + };
> > + };
> > + };
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + mipi_dsi_in: endpoint {
> > + remote-endpoint = <&lcdif_mipi_dsi>;
> > + };
> > + };
> > + port@1 {
> > + reg = <1>;
> > + mipi_dsi_out: endpoint {
> > + remote-endpoint = <&panel_in>;
> > + };
> > + };
> > + };
> > + };
> > --
> > 2.20.1
> >
>
Cheers and thanks again for having a look!
-- Guido
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