[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20190813155143.GA19830@bogus>
Date: Tue, 13 Aug 2019 09:51:43 -0600
From: Rob Herring <robh@...nel.org>
To: Chuanhong Guo <gch981213@...il.com>
Cc: "open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>,
"open list:MIPS" <linux-mips@...r.kernel.org>,
"open list:STAGING SUBSYSTEM" <devel@...verdev.osuosl.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>,
John Crispin <john@...ozen.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Weijie Gao <hackpascal@...il.com>, NeilBrown <neil@...wn.name>
Subject: Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding
documentation
On Wed, Jul 24, 2019 at 10:23:08AM +0800, Chuanhong Guo wrote:
> This commit adds device tree binding documentation for MT7621
> PLL controller.
>
> Signed-off-by: Chuanhong Guo <gch981213@...il.com>
> ---
>
> Change since v1:
> drop useless syscon in compatible string
>
> .../bindings/clock/mediatek,mt7621-pll.txt | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> new file mode 100644
> index 000000000000..7dcfbd5283e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt
> @@ -0,0 +1,18 @@
> +Binding for Mediatek MT7621 PLL controller
> +
> +The PLL controller provides the 2 main clocks of the SoC: CPU and BUS.
> +
> +Required Properties:
> +- compatible: has to be "mediatek,mt7621-pll"
> +- #clock-cells: has to be one
> +
> +Optional properties:
> +- clock-output-names: should be "cpu", "bus"
> +
> +Example:
> + pll {
> + compatible = "mediatek,mt7621-pll";
You didn't answer Stephen's question on v1.
Based on this binding, there is no way to control/program the PLL. Is
this part of some IP block?
> +
> + #clock-cells = <1>;
> + clock-output-names = "cpu", "bus";
> + };
> --
> 2.21.0
>
Powered by blists - more mailing lists