linux-kernel - Re: [PATCH 1/4] mailbox: arm_mhuv2: add device tree binding documentation

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Date:   Wed, 14 Aug 2019 11:05:18 +0100
From:   Sudeep Holla <sudeep.holla@....com>
To:     Jassi Brar <jassisinghbrar@...il.com>
Cc:     Morten Borup Petersen <morten_bp@...e.dk>,
        Tushar Khandelwal <tushar.khandelwal@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "tushar.2nov@...il.com" <tushar.2nov@...il.com>,
        "nd@....com" <nd@....com>,
        Morten Borup Petersen <morten.petersen@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Devicetree List <devicetree@...r.kernel.org>,
        Sudeep Holla <sudeep.holla@....com>
Subject: Re: [PATCH 1/4] mailbox: arm_mhuv2: add device tree binding
 documentation

On Tue, Aug 13, 2019 at 11:36:56AM -0500, Jassi Brar wrote:
[...]

> > >>
> > >> As mentioned in the response to your initial comment, the driver does
> > >> not currently support mixing protocols.
> > >>
> > > Thanks for acknowledging that limitation. But lets also address it.
> > >
> >
> > We are hesitant to dedicate time to developing mixing protocols given
> > that we don't have any current usecase nor any current platform which
> > would support this.
> >
> Can you please share the client code against which you tested this driver?
> From my past experience, I realise it is much more efficient to tidyup
> the code myself, than endlessly trying to explain the benefits.
>

Thanks for the patience and offer. Can we try the same with MHUv1 and SCMI
upstream driver.

The firmware just uses High Priority physical channel bit 0 and 2 as Tx
and bit 1 and 3 as Rx. Bit 2 and 3 are for perf which shouldn't get blocked
by bit 0 and 1. I mean I can have 10 requests covering clocks/sensors and
others on bit 0 and 1, but the bits 2 and 3 are dedicated for DVFS and
shouldn't be blocked because of other non DVFS requests.

The DT looks something like this(modified MHU binding for 2 cells)

	mailbox: mhu@...f0000 {
		compatible = "arm,primecell";
		reg = <0x0 0x2b1f0000 0x0 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mhu_lpri_rx",
				  "mhu_hpri_rx";
		#mbox-cells = <2>;
		mbox-name = "ARM-MHU";
		clocks = <&soc_refclk100mhz>;
		clock-names = "apb_pclk";
	};
	firmware {
		scmi {
			compatible = "arm,scmi";
			mbox-names = "tx", "rx";
			mboxes = <&mailbox 0 0 &mailbox 0 1>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_devpd: protocol@11 {
				reg = <0x11>;
				#power-domain-cells = <1>;
			};

			scmi_dvfs: protocol@13 {
				reg = <0x13>;
				#clock-cells = <1>;
				mbox-names = "tx", "rx";
				mboxes = <&mailbox 0 2 &mailbox 0 3>;
			};

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};

			scmi_sensors0: protocol@15 {
				reg = <0x15>;
				#thermal-sensor-cells = <1>;
			};
		};
	};

--
Regards,
Sudeep