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Message-ID: <1565779497-23621-2-git-send-email-sam.shih@mediatek.com>
Date: Wed, 14 Aug 2019 18:43:39 +0800
From: Sam Shih <sam.shih@...iatek.com>
To: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Thierry Reding <thierry.reding@...il.com>
CC: Ryder Lee <ryder.lee@...iatek.com>,
John Crispin <john@...ozen.org>, <linux-pwm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
sam shih <sam.shih@...iatek.com>
Subject: [PATCH v2 9/10] dt-bindings: pwm: update bindings for MT7628 SoC
From: sam shih <sam.shih@...iatek.com>
This updates bindings for MT7628 pwm controller.
Signed-off-by: Sam Shih <sam.shih@...iatek.com>
---
.../devicetree/bindings/pwm/pwm-mediatek.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
index c7bd5633d1eb..9d2d893a07ff 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
@@ -21,6 +21,8 @@ Required properties:
- pinctrl-0: One property must exist for each entry in pinctrl-names.
See pinctrl/pinctrl-bindings.txt for details of the property values.
- num-pwms: the number of PWM channels.
+ - clock-frequency: fix clock frequency, this is an optional property, only use in MT7628 SoC
+ for period calculation. This SoC has no complex clock tree.
Example:
pwm0: pwm@...06000 {
@@ -40,3 +42,13 @@ Example:
pinctrl-0 = <&pwm0_pins>;
num-pwms = <5>;
};
+MT7628 Example:
+ pwm: pwm@...0 {
+ compatible = "mediatek,mt7628-pwm";
+ reg = <0x5000 0x1000>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
+ num-pwms = <4>;
+ clock-frequency = <100000>;
+ };
--
2.17.1
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