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Message-Id: <20190815083716.4715-8-xiaowei.bao@nxp.com>
Date:   Thu, 15 Aug 2019 16:37:14 +0800
From:   Xiaowei Bao <xiaowei.bao@....com>
To:     jingoohan1@...il.com, gustavo.pimentel@...opsys.com,
        bhelgaas@...gle.com, robh+dt@...nel.org, mark.rutland@....com,
        shawnguo@...nel.org, leoyang.li@....com, kishon@...com,
        lorenzo.pieralisi@....com, arnd@...db.de,
        gregkh@...uxfoundation.org, minghuan.Lian@....com,
        mingkai.hu@....com, roy.zang@....com, linux-pci@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linuxppc-dev@...ts.ozlabs.org
Cc:     Xiaowei Bao <xiaowei.bao@....com>
Subject: [PATCH 08/10] dt-bindings: PCI: Add the pf-offset property

Add the pf-offset property for multiple PF.

Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
---
 Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c..d658687 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -43,6 +43,7 @@ RC mode:
 
 EP mode:
 - max-functions: maximum number of functions that can be configured
+- pf-offset: the offset of each PF's config space
 
 Example configuration:
 
-- 
2.9.5

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