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Message-Id: <27efba07aac2eb9b9ed719cfa2154326d515faa4.1565856842.git.rahul.tanwar@linux.intel.com>
Date: Thu, 15 Aug 2019 17:46:47 +0800
From: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
To: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de, hpa@...or.com,
x86@...nel.org
Cc: andriy.shevchenko@...el.com, alan@...ux.intel.com,
ricardo.neri-calderon@...ux.intel.com, rafael.j.wysocki@...el.com,
linux-kernel@...r.kernel.org, qi-ming.wu@...el.com,
cheol.yong.kim@...el.com, rahul.tanwar@...el.com,
Rahul Tanwar <rahul.tanwar@...ux.intel.com>
Subject: [PATCH 3/3] x86: arch: Add arch support for new Intel Atom CPU
This patch adds basic arch support for a new variant of Intel Atom CPU
model used in a network processor SoC named Lightning Mountain.
Signed-off-by: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
---
arch/x86/kernel/cpu/common.c | 1 +
arch/x86/kernel/cpu/intel.c | 1 +
arch/x86/kernel/tsc_msr.c | 5 +++++
3 files changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5cc2d51cc25e..c6b4a578b280 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
VULNWL_INTEL(CORE_YONAH, NO_SSB),
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
+ VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS),
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS),
VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS),
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0419fba1ea56..e989a8429390 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
case INTEL_FAM6_ATOM_SALTWELL_MID: /* Penwell */
case INTEL_FAM6_ATOM_SALTWELL_TABLET: /* Cloverview */
case INTEL_FAM6_ATOM_SILVERMONT_MID: /* Merrifield */
+ case INTEL_FAM6_ATOM_AIRMONT_NP: /* Lightning Mountain */
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
break;
default:
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858fe4db8..e0cbe4f2af49 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
};
+static const struct freq_desc freq_desc_lgm = {
+ 1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
+};
+
static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
@@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
+ INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_lgm),
{}
};
--
2.11.0
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