linux-kernel - Re: [PATCH v2 1/5] RISC-V: Remove per cpu clocksource

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <089a5ee46759074af391c50f5e9d28344b429de4.camel@wdc.com>
Date:   Fri, 16 Aug 2019 18:55:14 +0000
From:   Atish Patra <Atish.Patra@....com>
To:     "daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "palmer@...ive.com" <palmer@...ive.com>
CC:     "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        Anup Patel <Anup.Patel@....com>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "info@...ux.net" <info@...ux.net>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "allison@...utok.net" <allison@...utok.net>,
        "johan@...nel.org" <johan@...nel.org>,
        "alexios.zavras@...el.com" <alexios.zavras@...el.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>
Subject: Re: [PATCH v2 1/5] RISC-V: Remove per cpu clocksource

On Fri, 2019-08-16 at 17:09 +0200, Daniel Lezcano wrote:
> On 31/07/2019 03:24, Atish Patra wrote:
> > There is only one clocksource in RISC-V. The boot cpu initializes
> > that clocksource. No need to keep a percpu data structure.
> 
> That is not what is stated in the initial patch [1].
> 
> Can you clarify that ?
> 

I think what I meant to say was "There is only one clocksource used in
RISC-V Linux" as it is guranteed that all the timers across all the
harts are synchronized within one tick of each other [2]. 
Apologies for not being verbose here.

However, reading the privilege specification(1.12-draft) 

Section. 3.1.10 states that 

"Accurate real-time clocks (RTCs) are relatively expensive to provide
(requiring a crystal or MEMS oscillator) and have to run even when the
rest of system is powered down, and so there is usually only one in a
system located in a different frequency/voltage domain from the
processors. Hence, the RTC must be shared by all the harts in a system"

This is different from the commit text in [1].

Perhaps I misunderstood something. @Palmer ?


[2] 
https://elixir.bootlin.com/linux/v5.3-rc4/source/drivers/clocksource/timer-riscv.c#L44

> Thanks
> 
>   -- Daniel
> 
> [1] https://lkml.org/lkml/2018/8/4/51
> 
> 
> > Signed-off-by: Atish Patra <atish.patra@....com>
> > ---
> >  drivers/clocksource/timer-riscv.c | 6 ++----
> >  1 file changed, 2 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/clocksource/timer-riscv.c
> > b/drivers/clocksource/timer-riscv.c
> > index 5e6038fbf115..09e031176bc6 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void)
> >  	return get_cycles64();
> >  }
> >  
> > -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
> > +static struct clocksource riscv_clocksource = {
> >  	.name		= "riscv_clocksource",
> >  	.rating		= 300,
> >  	.mask		= CLOCKSOURCE_MASK(64),
> > @@ -92,7 +92,6 @@ void riscv_timer_interrupt(void)
> >  static int __init riscv_timer_init_dt(struct device_node *n)
> >  {
> >  	int cpuid, hartid, error;
> > -	struct clocksource *cs;
> >  
> >  	hartid = riscv_of_processor_hartid(n);
> >  	if (hartid < 0) {
> > @@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct
> > device_node *n)
> >  
> >  	pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
> >  	       __func__, cpuid, hartid);
> > -	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
> > -	error = clocksource_register_hz(cs, riscv_timebase);
> > +	error = clocksource_register_hz(&riscv_clocksource,
> > riscv_timebase);
> >  	if (error) {
> >  		pr_err("RISCV timer register failed [%d] for cpu =
> > [%d]\n",
> >  		       error, cpuid);
> > 
> 
>