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Message-Id: <20190817034612.6DA7E21721@mail.kernel.org>
Date: Fri, 16 Aug 2019 20:46:11 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: mturquette@...libre.com, robh+dt@...nel.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
haitao.suo@...main.com, darren.tsao@...main.com,
fisher.cheng@...main.com, alec.lin@...main.com
Subject: Re: [PATCH 1/5] dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding
Quoting Manivannan Sadhasivam (2019-08-16 20:34:22)
> On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2019-07-05 08:14:36)
> > > +It is expected that it is defined using standard clock bindings as "osc".
> > > +
> > > +Example:
> > > +
> > > + clk: clock-controller@800 {
> > > + compatible = "bitmain,bm1880-clk";
> > > + reg = <0xe8 0x0c>,<0x800 0xb0>;
> >
> > It looks weird still. What hardware module is this actually part of?
> > Some larger power manager block?
> >
>
> These are all part of the sysctrl block (clock + pinctrl + reset) and the
> register domains got split between system and pll.
>
And that can't be one node that probes the clk, pinctrl, and reset
drivers from C code?
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