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Date:   Tue, 20 Aug 2019 22:24:44 +0000
From:   Atish Patra <Atish.Patra@....com>
To:     "hch@...radead.org" <hch@...radead.org>
CC:     "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "schwab@...ux-m68k.org" <schwab@...ux-m68k.org>,
        "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
        "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "allison@...utok.net" <allison@...utok.net>,
        "anup@...infault.org" <anup@...infault.org>,
        "palmer@...ive.com" <palmer@...ive.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [v2 PATCH] RISC-V: Optimize tlb flush path.

On Tue, 2019-08-20 at 15:18 -0700, hch@...radead.org wrote:
> CAUTION: This email originated from outside of Western Digital. Do
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> 
> 
> On Tue, Aug 20, 2019 at 08:28:36PM +0000, Atish Patra wrote:
> > > http://git.infradead.org/users/hch/riscv.git/commitdiff/ea4067ae61e20fcfcf46a6f6bd1cc25710ce3afe
> > 
> > This does seem a lot cleaner to me. We can reuse some of the code
> > for
> > this patch as well. Based on NATIVE_CLINT configuration, it will
> > send
> > an IPI or SBI call.
> > 
> > I can rebase my patch on top of yours and I can send it together or
> > you
> > can include in your series.
> > 
> > Let me know your preference.
> 
> I think the native clint for S-mode will need more discussion, so you
> should not wait for it.

Ok sure. I will move the code to tlbflush.c and refactor the tlb flush
functions similar to what you have in your patch.

-- 
Regards,
Atish

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