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Message-Id: <fa6b20015dc6bfe247e1b2a07bdc5c727595a04b.1566288689.git.rahul.tanwar@linux.intel.com>
Date: Tue, 20 Aug 2019 16:29:02 +0800
From: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
To: robh+dt@...nel.org, devicetree@...r.kernel.org,
gregkh@...uxfoundation.org, mark.rutland@....com,
linux-serial@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, andriy.shevchenko@...el.com,
qi-ming.wu@...el.com, cheol.yong.kim@...el.com,
rahul.tanwar@...el.com, Rahul Tanwar <rahul.tanwar@...ux.intel.com>
Subject: [PATCH v2 2/2] dt-bindings: lantiq: Update for new SoC
Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
Update the dt bindings to support LGM as well.
Signed-off-by: Rahul Tanwar <rahul.tanwar@...ux.intel.com>
---
.../devicetree/bindings/serial/lantiq_asc.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
index 54b90490f4fb..92807b59b024 100644
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
@@ -17,6 +17,7 @@ properties:
oneOf:
items:
- const: lantiq,asc
+ - const: intel,lgm-asc
reg:
maxItems: 1
@@ -28,6 +29,12 @@ properties:
- description: tx or combined interrupt
- description: rx interrupt
- description: err interrupt
+ description:
+ For lantiq,asc compatible, it supports 3 separate
+ interrupts for tx rx & err. Whereas, for intel,lgm-asc
+ compatible, it supports combined single interrupt for
+ all of tx, rx & err interrupts.
+
clocks:
description:
@@ -67,4 +74,14 @@ examples:
interrupts = <112 113 114>;
};
+ - |
+ asc0: serial@...00000 {
+ compatible = "intel,lgm-asc";
+ reg = <0xe0a00000 0x1000>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <128 1>;
+ clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
+ clock-names = "freq", "asc";
+ };
+
...
--
2.11.0
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