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Message-ID: <20190820011255.GD5599@leoy-ThinkPad-X240s>
Date: Tue, 20 Aug 2019 09:12:55 +0800
From: Leo Yan <leo.yan@...aro.org>
To: Arnaldo Carvalho de Melo <arnaldo.melo@...il.com>
Cc: Mathieu Poirier <mathieu.poirier@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Mike Leach <mike.leach@...aro.org>,
Robert Walker <robert.walker@....com>,
Coresight ML <coresight@...ts.linaro.org>
Subject: Re: [PATCH 1/2] perf cs-etm: Support sample flags 'insn' and
'insnlen'
On Mon, Aug 19, 2019 at 03:50:54PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Mon, Aug 19, 2019 at 12:08:26PM -0600, Mathieu Poirier escreveu:
> > On Thu, 15 Aug 2019 at 02:30, Leo Yan <leo.yan@...aro.org> wrote:
> > >
> > > The synthetic branch and instruction samples are missed to set
> > > instruction related info, thus perf tool fails to display samples with
> > > flags '-F,+insn,+insnlen'.
> > >
> > > CoreSight trace decoder has provided sufficient information to decide
> > > the instruction size based on the isa type: A64/A32 instruction are
> > > 32-bit size, but one exception is the T32 instruction size, which might
> > > be 32-bit or 16-bit.
> > >
> > > This patch handles for these cases and it reads the instruction values
> > > from DSO file; thus can support flags '-F,+insn,+insnlen'.
>
> > The code seems to be correct. I have also tested this patch.
>
> > Reviewed-by: Mathieu Poirier <mathieu.poirier@...aro.org>
>
> Thanks, applied.
Thanks a lot, Mathieu & Arnaldo.
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