[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <VI1PR04MB70239C63D88ED27D929E29C1EEAA0@VI1PR04MB7023.eurprd04.prod.outlook.com>
Date: Wed, 21 Aug 2019 20:39:56 +0000
From: Leonard Crestez <leonard.crestez@....com>
To: Daniel Baluta <daniel.baluta@....com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
Abel Vesa <abel.vesa@....com>
CC: "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
dl-linux-imx <linux-imx@....com>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"ccaione@...libre.com" <ccaione@...libre.com>,
"baruch@...s.co.il" <baruch@...s.co.il>,
"andrew.smirnov@...il.com" <andrew.smirnov@...il.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"S.j. Wang" <shengjiu.wang@....com>,
"angus@...ea.ca" <angus@...ea.ca>,
"agx@...xcpu.org" <agx@...xcpu.org>,
Anson Huang <anson.huang@....com>, Peng Fan <peng.fan@....com>,
Jacky Bai <ping.bai@....com>,
Stephen Boyd <sboyd@...eaurora.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for
clocks
On 28.07.2019 18:20, Daniel Baluta wrote:
> From: Abel Vesa <abel.vesa@....com>
>
> Add the initial configuration for clocks that need default parent and rate
> setting. This is based on the vendor tree clock provider parents and rates
> configuration except this is doing the setup in dts rather then using clock
> consumer API in a clock provider driver.
>
> Note that by adding the initial rate setting for audio_pll1/audio_pll
> setting we need to remove it from imx8mq-librem5-devkit.dts
Setting default rates for audio_pll1 and audio_pll2 in soc dtsi makes a
lot of sense to me; the intention is for one to run at a multiple of
44.1k and another at a multiple of 48k.
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 02fbd0625318..a55d72ba2e05 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -494,6 +494,25 @@
> clock-names = "ckil", "osc_25m", "osc_27m",
> "clk_ext1", "clk_ext2",
> "clk_ext3", "clk_ext4";
> + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL2>,
> + <&clk IMX8MQ_CLK_AHB>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
> + <&clk IMX8MQ_CLK_AUDIO_AHB>,
> + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
> + <&clk IMX8MQ_CLK_NOC>;
> + assigned-clock-parents = <0>,
> + <0>,
> + <0> > + <&clk IMX8MQ_SYS1_PLL_133M>,
> + <&clk IMX8MQ_SYS1_PLL_266M>,
> + <&clk IMX8MQ_SYS2_PLL_500M>,
> + <&clk IMX8MQ_CLK_27M>,
> + <&clk IMX8MQ_SYS1_PLL_800M>;
> + assigned-clock-rates = <593999999>,
> + <786432000>,
> + <722534400>;
The audio PLLs should run below 650 mHz so please use 393216000 and
361267200 instead of 786432000 and 722534400. For the 8mm equivalent see
commit 053a4ffe2988 ("clk: imx: imx8mm: fix audio pll setting").
You should also move the unbypassing of AUDIO_PLL1 and AUDIO_PLL2 here
just add two more assigned-clocks and assigned-clock-parents.
--
Regards,
Leonard
Powered by blists - more mailing lists