linux-kernel - Re: [v2 PATCH] RISC-V: Optimize tlb flush path.

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Message-ID: <20190821071855.GA32145@infradead.org>
Date:   Wed, 21 Aug 2019 00:18:55 -0700
From:   "hch@...radead.org" <hch@...radead.org>
To:     Anup Patel <anup@...infault.org>
Cc:     "hch@...radead.org" <hch@...radead.org>,
        Alan Kao <alankao@...estech.com>,
        Atish Patra <Atish.Patra@....com>,
        "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "palmer@...ive.com" <palmer@...ive.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "schwab@...ux-m68k.org" <schwab@...ux-m68k.org>,
        "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "allison@...utok.net" <allison@...utok.net>
Subject: Re: [v2 PATCH] RISC-V: Optimize tlb flush path.

On Wed, Aug 21, 2019 at 09:22:48AM +0530, Anup Patel wrote:
> I agree that IPI mechanism should be standardized for RISC-V but I
> don't support the idea of mandating CLINT as part of the UNIX
> platform spec. For example, the AndesTech SOC does not use CLINT
> instead they have PLMT for per-HART timer and PLICSW for per-HART
> IPIs.

The point is not really mandating a CLINT as know right now.  The
point is to mandate one way to issue IPIs from S-mode to S-mode,
one way to read the time counter and one way to write the timer
threshold.