linux-kernel - Re: [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer operation

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Message-ID: <744188a1-d11a-7edc-79cd-e3c7dbcf6e86@linaro.org>
Date:   Wed, 21 Aug 2019 12:11:19 +0200
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     Avi Fishman <avifishman70@...il.com>, tmaimon77@...il.com,
        tali.perry1@...il.com, venture@...gle.com, yuenn@...gle.com,
        benjaminfair@...gle.com, tglx@...utronix.de
Cc:     openbmc@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] [v5] clocksource/drivers/npcm: fix GENMASK and timer
 operation

On 29/07/2019 19:03, Avi Fishman wrote:
> NPCM7XX_Tx_OPER GENMASK bits where wrong,
> Since NPCM7XX_REG_TICR0 register reset value of those bits was 0,
> it did not cause an issue.
> in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
> read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
> take effect.
> 
> npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
> in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
> confusing.
> npcm7xx_timer_oneshot() did wrong calculation
> 
> Signed-off-by: Avi Fishman <avifishman70@...il.com>

I've applied the patch and massaged the changelog [1].

Let me know if you disagree with it.

Please, in the future take care of adding the Fixes tag.

Thanks

  -- Daniel

[1]
https://git.linaro.org/people/daniel.lezcano/linux.git/commit/?h=clockevents/next&id=a5f6679fc81e42fcbef0184770d8a3b04c0f153e

> ---
>  drivers/clocksource/timer-npcm7xx.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c
> index 8a30da7f083b..9780ffd8010e 100644
> --- a/drivers/clocksource/timer-npcm7xx.c
> +++ b/drivers/clocksource/timer-npcm7xx.c
> @@ -32,7 +32,7 @@
>  #define NPCM7XX_Tx_INTEN		BIT(29)
>  #define NPCM7XX_Tx_COUNTEN		BIT(30)
>  #define NPCM7XX_Tx_ONESHOT		0x0
> -#define NPCM7XX_Tx_OPER			GENMASK(27, 3)
> +#define NPCM7XX_Tx_OPER			GENMASK(28, 27)
>  #define NPCM7XX_Tx_MIN_PRESCALE		0x1
>  #define NPCM7XX_Tx_TDR_MASK_BITS	24
>  #define NPCM7XX_Tx_MAX_CNT		0xFFFFFF
> @@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt)
>  
>  	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  	val &= ~NPCM7XX_Tx_OPER;
> -
> -	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  	val |= NPCM7XX_START_ONESHOT_Tx;
>  	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  
> @@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt)
>  	struct timer_of *to = to_timer_of(evt);
>  	u32 val;
>  
> +	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
> +
>  	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  	val &= ~NPCM7XX_Tx_OPER;
> -
> -	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
>  	val |= NPCM7XX_START_PERIODIC_Tx;
> -
>  	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
>  
>  	return 0;
> 


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