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Message-ID: <2d690bc4d00a3b911d7c50a909aa7f27870ea092.camel@yadro.com>
Date:   Wed, 21 Aug 2019 18:45:36 +0300
From:   Ivan Mikhaylov <i.mikhaylov@...ro.com>
To:     Wim Van Sebroeck <wim@...ux-watchdog.org>,
        Guenter Roeck <linux@...ck-us.net>
CC:     Joel Stanley <joel@....id.au>, Andrew Jeffery <andrew@...id.au>,
        <linux-watchdog@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-aspeed@...ts.ozlabs.org>, <linux-kernel@...r.kernel.org>,
        "Alexander Amelkin" <a.amelkin@...ro.com>
Subject: 

>From 1687adb615ceb7a4013712604f177dc906059667 Mon Sep 17 00:00:00 2001
From: Ivan Mikhaylov <i.mikhaylov@...ro.com>
Date: Wed, 21 Aug 2019 18:21:05 +
Subject: [PATCH 0/3] add dual-boot support

ASPEED SoCs support dual-boot feature for SPI Flash.
When strapped appropriately, the SoC starts wdt2 (/dev/watchdog1)
and if within a minute it is not disabled, it goes off and reboots
the SoC from an alternate SPI Flash chip by changing CS0 controls
to actually drive CS1 line.

When booted from alternate chip, in order to access the main chip
at CS0, the user must reset the appropriate bit in the watchdog
hardware. There is no interface that would allow to do that from
an embedded firmware startup script.

This commit implements support for that feature:

* Enable 'alt-boot' option for wdt2

* Enable secondary SPI flash chip

* Make it possible to get access to the primary SPI flash chip at CS0
  after booting from the alternate chip at CS1. A sysfs interface is added
  to provide an easy way for embedded firmware startup scripts to clear
  the chip select bit to gain access to the primary flash chip in order
  to allow for recovery of its contents.

Ivan Mikhaylov (3):
  vesnin: add wdt2 section with alt-boot option
  vesnin: add secondary SPI flash chip
  watchdog/aspeed: add support for dual boot

 arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 12 +++++++++
 drivers/watchdog/aspeed_wdt.c               | 30 +++++++++++++++++++++
 2 files changed, 42 insertions(+)

-- 
2.20.1