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Date: Tue, 20 Aug 2019 22:07:55 -0400 From: Anson Huang <Anson.Huang@....com> To: wim@...ux-watchdog.org, linux@...ck-us.net, robh+dt@...nel.org, mark.rutland@....com, shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com, linux@...linux.org.uk, otavio@...ystems.com.br, leonard.crestez@....com, schnitzeltony@...il.com, u.kleine-koenig@...gutronix.de, jan.tuerk@...rion.com, linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Cc: Linux-imx@....com Subject: [PATCH V3 1/4] dt-bindings: watchdog: Add i.MX7ULP bindings Add the watchdog bindings for Freescale i.MX7ULP. Signed-off-by: Anson Huang <Anson.Huang@....com> --- No changes. --- .../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt new file mode 100644 index 0000000..d83fc5c --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt @@ -0,0 +1,22 @@ +* Freescale i.MX7ULP Watchdog Timer (WDT) Controller + +Required properties: +- compatible : Should be "fsl,imx7ulp-wdt" +- reg : Should contain WDT registers location and length +- interrupts : Should contain WDT interrupt +- clocks: Should contain a phandle pointing to the gated peripheral clock. + +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + +Examples: + +wdog1: wdog@...d0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; +}; -- 2.7.4
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