[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <c358a18b99a59ff600f83dd0c83ad80072f3d10b.camel@infinera.com>
Date: Thu, 22 Aug 2019 07:05:57 +0000
From: Joakim Tjernlund <Joakim.Tjernlund@...inera.com>
To: "christophe.leroy@....fr" <christophe.leroy@....fr>,
"paulus@...ba.org" <paulus@...ba.org>,
"mpe@...erman.id.au" <mpe@...erman.id.au>,
"benh@...nel.crashing.org" <benh@...nel.crashing.org>
CC: "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] powerpc/8xx: drop unused self-modifying code alternative
to FixupDAR.
On Wed, 2019-08-21 at 20:00 +0000, Christophe Leroy wrote:
>
> The code which fixups the DAR on TLB errors for dbcX instructions
> has a self-modifying code alternative that has never been used.
>
> Drop it.
Argh, my master piece from way back :)
But it is time for it to go.
Reviewed-by: Joakim Tjernlund <joakim.tjernlund@...inera.com>
Jocke
>
> Signed-off-by: Christophe Leroy <christophe.leroy@....fr>
> ---
> arch/powerpc/kernel/head_8xx.S | 24 ------------------------
> 1 file changed, 24 deletions(-)
>
> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
> index b8ca5b43e587..19f583e18402 100644
> --- a/arch/powerpc/kernel/head_8xx.S
> +++ b/arch/powerpc/kernel/head_8xx.S
> @@ -575,8 +575,6 @@ InstructionBreakpoint:
> * by decoding the registers used by the dcbx instruction and adding them.
> * DAR is set to the calculated address.
> */
> - /* define if you don't want to use self modifying code */
> -#define NO_SELF_MODIFYING_CODE
> FixupDAR:/* Entry point for dcbx workaround. */
> mtspr SPRN_M_TW, r10
> /* fetch instruction from memory. */
> @@ -640,27 +638,6 @@ FixupDAR:/* Entry point for dcbx workaround. */
> rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
> mtspr SPRN_DSISR, r10
> 142: /* continue, it was a dcbx, dcbi instruction. */
> -#ifndef NO_SELF_MODIFYING_CODE
> - andis. r10,r11,0x1f /* test if reg RA is r0 */
> - li r10,modified_instr@l
> - dcbtst r0,r10 /* touch for store */
> - rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
> - oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
> - ori r11,r11,532
> - stw r11,0(r10) /* store add/and instruction */
> - dcbf 0,r10 /* flush new instr. to memory. */
> - icbi 0,r10 /* invalidate instr. cache line */
> - mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
> - mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
> - isync /* Wait until new instr is loaded from memory */
> -modified_instr:
> - .space 4 /* this is where the add instr. is stored */
> - bne+ 143f
> - subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
> -143: mtdar r10 /* store faulting EA in DAR */
> - mfspr r10,SPRN_M_TW
> - b DARFixed /* Go back to normal TLB handling */
> -#else
> mfctr r10
> mtdar r10 /* save ctr reg in DAR */
> rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
> @@ -724,7 +701,6 @@ modified_instr:
> add r10, r10, r11 /* add it */
> mfctr r11 /* restore r11 */
> b 151b
> -#endif
>
> /*
> * This is where the main kernel code starts.
> --
> 2.13.3
>
Powered by blists - more mailing lists