linux-kernel - Re: [PATCH v3 4/4] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

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Message-ID: <CY4PR2201MB1272F47798E4002689E89D01C1A70@CY4PR2201MB1272.namprd22.prod.outlook.com>
Date:   Sat, 24 Aug 2019 14:13:54 +0000
From:   Paul Burton <paul.burton@...s.com>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
CC:     "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "john@...ozen.org" <john@...ozen.org>,
        "kishon@...com" <kishon@...com>,
        Paul Burton <pburton@...ecomp.com>,
        "ralf@...ux-mips.org" <ralf@...ux-mips.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "hauke@...ke-m.de" <hauke@...ke-m.de>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "ms@....tdt.de" <ms@....tdt.de>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>
Subject: Re: [PATCH v3 4/4] MIPS: lantiq: update the clock alias' for the
 mainline  PCIe PHY driver

Hello,

Martin Blumenstingl wrote:
> The mainline PCIe PHY driver has it's own devicetree node. Update the
> clock alias so the mainline driver finds the clocks.
> 
> The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
> and GRX390.
> The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
> GRX390.
> The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
> Lantiq's board support package (called "UGW") names these registers
> "PDI".

Applied to mips-next.

> commit ed90302be64a
> https://git.kernel.org/mips/c/ed90302be64a
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> Signed-off-by: Paul Burton <paul.burton@...s.com>

Thanks,
    Paul

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