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Message-ID: <CADnq5_OgDuFm_Huofu6S2O2dyzO42UdZm=cYgRKwH7f4gTCyvg@mail.gmail.com>
Date: Mon, 26 Aug 2019 11:18:22 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Harry Wentland <hwentlan@....com>
Cc: YueHaibing <yuehaibing@...wei.com>,
"Wentland, Harry" <Harry.Wentland@....com>,
"Li, Sun peng (Leo)" <Sunpeng.Li@....com>,
"Deucher, Alexander" <Alexander.Deucher@....com>,
"Koenig, Christian" <Christian.Koenig@....com>,
"Zhou, David(ChunMing)" <David1.Zhou@....com>,
"airlied@...ux.ie" <airlied@...ux.ie>,
"daniel@...ll.ch" <daniel@...ll.ch>, "Lei, Jun" <Jun.Lei@....com>,
"Laktyushkin, Dmytro" <Dmytro.Laktyushkin@....com>,
"Lakha, Bhawanpreet" <Bhawanpreet.Lakha@....com>,
"Aberback, Joshua" <Joshua.Aberback@....com>,
"Liu, Wenjing" <Wenjing.Liu@....com>,
"Liu, Charlene" <Charlene.Liu@....com>,
"Leung, Martin" <Martin.Leung@....com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"amd-gfx@...ts.freedesktop.org" <amd-gfx@...ts.freedesktop.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH -next] drm/amdgpu/display: fix build error without CONFIG_DRM_AMD_DC_DSC_SUPPORT
On Mon, Aug 26, 2019 at 9:22 AM Harry Wentland <hwentlan@....com> wrote:
>
>
>
> On 2019-08-26 4:57 a.m., YueHaibing wrote:
> > If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct:
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28:
> > error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control?
> > dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
> > ^~~~~~~~~~~~~~~~~~~~
> > dcn20_dpp_pg_control
> >
> > Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this.
> >
> > Reported-by: Hulk Robot <hulkci@...wei.com>
> > Fixes: 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot")
> > Signed-off-by: YueHaibing <yuehaibing@...wei.com>
>
> Reviewed-by: Harry Wentland <harry.wentland@....com>
>
Applied. Thanks,
Alex
> Harry
>
> > ---
> > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index e146d1d..54d67f6 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -2092,7 +2092,11 @@ void dcn20_hw_sequencer_construct(struct dc *dc)
> > dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
> > dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
> > dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
> > +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> > dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
> > +#else
> > + dc->hwss.dsc_pg_control = NULL;
> > +#endif
> > dc->hwss.disable_vga = dcn20_disable_vga;
> >
> > if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
> >
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