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Message-ID: <20190827172151.GA31588@roeck-us.net>
Date: Tue, 27 Aug 2019 10:21:52 -0700
From: Guenter Roeck <linux@...ck-us.net>
To: Ivan Mikhaylov <i.mikhaylov@...ro.com>
Cc: Wim Van Sebroeck <wim@...ux-watchdog.org>,
Joel Stanley <joel@....id.au>,
Andrew Jeffery <andrew@...id.au>,
linux-watchdog@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org,
Alexander Amelkin <a.amelkin@...ro.com>,
openbmc@...ts.ozlabs.org, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, devicetree@...r.kernel.org
Subject: Re: [PATCH v3 3/4] watchdog/aspeed: add support for dual boot
On Tue, Aug 27, 2019 at 07:54:25PM +0300, Ivan Mikhaylov wrote:
> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
> to clear out boot code source and re-enable access to the primary SPI flash
> chip while booted via wdt2 from the alternate chip.
>
> AST2400 datasheet says:
> "In the 2nd flash booting mode, all the address mapping to CS0# would be
> re-directed to CS1#. And CS0# is not accessable under this mode. To access
> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
> register WDT30.bit[1]."
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@...ro.com>
Please run "checkpatch --strict" on this patch and fix the reported problems
(I _did_ ask for proper multi-line aligment before, but there are a couple
of other issues as well).
Thanks,
Guenter
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