linux-kernel - Re: [PATCH v2 0/5] 0/6] arm64: meson-sm1: add support for DVFS

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7h1rx6uti8.fsf@baylibre.com>
Date:   Tue, 27 Aug 2019 15:35:11 -0700
From:   Kevin Hilman <khilman@...libre.com>
To:     Jerome Brunet <jbrunet@...libre.com>,
        Neil Armstrong <narmstrong@...libre.com>
Cc:     Neil Armstrong <narmstrong@...libre.com>,
        linux-clk@...r.kernel.org, linux-amlogic@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 0/5] 0/6] arm64: meson-sm1: add support for DVFS

Kevin Hilman <khilman@...libre.com> writes:

> Jerome Brunet <jbrunet@...libre.com> writes:
>
>> On Mon 26 Aug 2019 at 09:25, Neil Armstrong <narmstrong@...libre.com> wrote:
>>
>>> Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
>>> enables DVFS on the SM1 SoC for the SEI610 board.
>>>
>>> The SM1 Clock structure is slightly different because of the Cortex-A55
>>> core used, having the capability for each core of a same cluster to run
>>> at a different frequency thanks to the newly used DynamIQ Shared Unit.
>>>
>>> This is why SM1 has a CPU clock tree for each core and for DynamIQ Shared Unit,
>>> with a bypass mux to use the CPU0 instead of the dedicated trees.
>>>
>>> The DSU uses a new GP1 PLL as default clock, thus GP1 is added as read-only.
>>>
>>> The SM1 OPPs has been taken from the Amlogic Vendor tree, and unlike
>>> G12A only a single version of the SoC is available.
>>>
>>> Dependencies:
>>> - patch 6 is based on the "arm64: meson: add support for SM1 Power Domains" serie,
>>> 	but is not a strong dependency, it will work without
>>>
>>> Changes since v1:
>>> - exposed GP1, DSU and CPU 1,2,3 clock in patch 1
>>>
>>> Neil Armstrong (5):
>>>   dt-bindings: clk: meson: add sm1 periph clock controller bindings
>>>   clk: meson: g12a: add support for SM1 GP1 PLL
>>>   clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
>>>   clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
>>>   arm64: dts: meson-sm1-sei610: enable DVFS
>>>
>>>  .../bindings/clock/amlogic,gxbb-clkc.txt      |   1 +
>>>  .../boot/dts/amlogic/meson-sm1-sei610.dts     |  59 +-
>>>  arch/arm64/boot/dts/amlogic/meson-sm1.dtsi    |  69 +++
>>>  drivers/clk/meson/g12a.c                      | 544 ++++++++++++++++++
>>>  drivers/clk/meson/g12a.h                      |  24 +-
>>>  include/dt-bindings/clock/g12a-clkc.h         |   5 +
>>>  6 files changed, 697 insertions(+), 5 deletions(-)
>>
>> Applied 1 to 4
>
> Will there be a stable tag I can use for that so I can apply patch 5?

Ah, I should've finished reading the list before asking.  I now see your
clock PR.  I'll use this tag[1] unless there's a different one I should
use.

Kevin

[1] git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.4-2