| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 27 Aug 2019 10:58:32 +0300
From: Mike Rapoport <rppt@...ux.ibm.com>
To: Atish Patra <atish.patra@....com>
Cc: linux-kernel@...r.kernel.org, Albert Ou <aou@...s.berkeley.edu>,
Alan Kao <alankao@...estech.com>,
Alexios Zavras <alexios.zavras@...el.com>,
Anup Patel <anup@...infault.org>,
Palmer Dabbelt <palmer@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Gary Guo <gary@...yguo.net>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-riscv@...ts.infradead.org,
Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [RFC PATCH 2/2] RISC-V: Add basic support for SBI v0.2
On Mon, Aug 26, 2019 at 04:32:56PM -0700, Atish Patra wrote:
> The SBI v0.2 introduces a base extension which is backward compatible
> with v0.1. Implement all helper functions and minimum required SBI
> calls from v0.2 for now. All other base extension function will be
> added later as per need.
>
> Signed-off-by: Atish Patra <atish.patra@....com>
> ---
> arch/riscv/include/asm/sbi.h | 68 +++++++++++++++++++++++++++++-------
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/kernel/sbi.c | 50 ++++++++++++++++++++++++++
> arch/riscv/kernel/setup.c | 2 ++
> 4 files changed, 108 insertions(+), 13 deletions(-)
> create mode 100644 arch/riscv/kernel/sbi.c
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 7f5ecaaaa0d7..4a4476956693 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -8,7 +8,6 @@
>
> #include <linux/types.h>
>
> -
> #define SBI_EXT_LEGACY_SET_TIMER 0x0
> #define SBI_EXT_LEGACY_CONSOLE_PUTCHAR 0x1
> #define SBI_EXT_LEGACY_CONSOLE_GETCHAR 0x2
> @@ -19,28 +18,61 @@
> #define SBI_EXT_LEGACY_REMOTE_SFENCE_VMA_ASID 0x7
> #define SBI_EXT_LEGACY_SHUTDOWN 0x8
>
> -#define SBI_CALL_LEGACY(which, arg0, arg1, arg2, arg3) ({ \
> +#define SBI_EXT_BASE 0x10
> +
> +enum sbi_ext_base_fid {
> + SBI_EXT_BASE_GET_SPEC_VERSION = 0,
> + SBI_EXT_BASE_GET_IMP_ID,
> + SBI_EXT_BASE_GET_IMP_VERSION,
> + SBI_EXT_BASE_PROBE_EXT,
> + SBI_EXT_BASE_GET_MVENDORID,
> + SBI_EXT_BASE_GET_MARCHID,
> + SBI_EXT_BASE_GET_MIMPID,
> +};
> +
> +#define SBI_CALL_LEGACY(ext, fid, arg0, arg1, arg2, arg3) ({ \
> register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); \
> - register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); \
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); \
> asm volatile ("ecall" \
> - : "+r" (a0) \
> - : "r" (a1), "r" (a2), "r" (a3), "r" (a7) \
> + : "+r" (a0), "+r" (a1) \
> + : "r" (a2), "r" (a3), "r" (a6), "r" (a7) \
Maybe I'm missing something, but how is this supposed to work on systems
with SBI v0.1? Wouldn't this cause a mismatch in the registers?
> : "memory"); \
> a0; \
> })
>
> /* Lazy implementations until SBI is finalized */
> -#define SBI_CALL_LEGACY_0(which) SBI_CALL_LEGACY(which, 0, 0, 0, 0)
> -#define SBI_CALL_LEGACY_1(which, arg0) SBI_CALL_LEGACY(which, arg0, 0, 0, 0)
> -#define SBI_CALL_LEGACY_2(which, arg0, arg1) \
> - SBI_CALL_LEGACY(which, arg0, arg1, 0, 0)
> -#define SBI_CALL_LEGACY_3(which, arg0, arg1, arg2) \
> - SBI_CALL_LEGACY(which, arg0, arg1, arg2, 0)
> -#define SBI_CALL_LEGACY_4(which, arg0, arg1, arg2, arg3) \
> - SBI_CALL_LEGACY(which, arg0, arg1, arg2, arg3)
> +#define SBI_CALL_LEGACY_0(ext) SBI_CALL_LEGACY(ext, 0, 0, 0, 0, 0)
> +#define SBI_CALL_LEGACY_1(ext, arg0) SBI_CALL_LEGACY(ext, 0, arg0, 0, 0, 0)
> +#define SBI_CALL_LEGACY_2(ext, arg0, arg1) \
> + SBI_CALL_LEGACY(ext, 0, arg0, arg1, 0, 0)
> +#define SBI_CALL_LEGACY_3(ext, arg0, arg1, arg2) \
> + SBI_CALL_LEGACY(ext, 0, arg0, arg1, arg2, 0)
> +#define SBI_CALL_LEGACY_4(ext, arg0, arg1, arg2, arg3) \
> + SBI_CALL_LEGACY(ext, 0, arg0, arg1, arg2, arg3)
> +
> +extern unsigned long sbi_firmware_version;
> +struct sbiret {
> + long error;
> + long value;
> +};
> +
> +void riscv_sbi_init(void);
> +struct sbiret riscv_sbi_ecall(int ext, int fid, int arg0, int arg1,
> + int arg2, int arg3);
> +
> +#define SBI_CALL_0(ext, fid) riscv_sbi_ecall(ext, fid, 0, 0, 0, 0)
> +#define SBI_CALL_1(ext, fid, arg0) riscv_sbi_ecall(ext, fid, arg0, 0, 0, 0)
> +#define SBI_CALL_2(ext, fid, arg0, arg1) \
> + riscv_sbi_ecall(ext, fid, arg0, arg1, 0, 0)
> +#define SBI_CALL_3(ext, fid, arg0, arg1, arg2) \
> + riscv_sbi_ecall(ext, fid, arg0, arg1, arg2, 0)
> +#define SBI_CALL_4(ext, fid, arg0, arg1, arg2, arg3) \
> + riscv_sbi_ecall(ext, fid, arg0, arg1, arg2, arg3)
> +
>
> static inline void sbi_console_putchar(int ch)
> {
> @@ -99,4 +131,14 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> start, size, asid);
> }
>
> +static inline unsigned long riscv_sbi_major_version(void)
> +{
> + return (sbi_firmware_version >> 24) & 0x7f;
> +}
> +
> +static inline unsigned long riscv_sbi_minor_version(void)
> +{
> + return sbi_firmware_version & 0xffffff;
> +}
> +
> #endif
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index 2420d37d96de..faf862d26924 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -17,6 +17,7 @@ obj-y += irq.o
> obj-y += process.o
> obj-y += ptrace.o
> obj-y += reset.o
> +obj-y += sbi.o
> obj-y += setup.o
> obj-y += signal.o
> obj-y += syscall_table.o
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> new file mode 100644
> index 000000000000..457b8cc0e9d9
> --- /dev/null
> +++ b/arch/riscv/kernel/sbi.c
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * SBI initialilization and base extension implementation.
> + *
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> + */
> +
> +#include <asm/sbi.h>
> +#include <linux/sched.h>
> +
> +unsigned long sbi_firmware_version;
> +
> +struct sbiret riscv_sbi_ecall(int ext, int fid, int arg0, int arg1,
> + int arg2, int arg3)
> +{
> + struct sbiret ret;
> +
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> + asm volatile ("ecall"
> + : "+r" (a0), "+r" (a1)
> + : "r" (a2), "r" (a3), "r" (a6), "r" (a7)
> + : "memory");
> + ret.error = a0;
> + ret.value = a1;
> +
> + return ret;
> +}
> +
> +static struct sbiret sbi_get_spec_version(void)
> +{
> + return SBI_CALL_0(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION);
> +}
> +
> +void riscv_sbi_init(void)
> +{
> + struct sbiret ret;
> +
> + /* legacy SBI version*/
> + sbi_firmware_version = 0x1;
> + ret = sbi_get_spec_version();
> + if (!ret.error)
> + sbi_firmware_version = ret.value;
> + pr_info("SBI version implemented in firmware [%lu:%lu]\n",
> + riscv_sbi_major_version(), riscv_sbi_minor_version());
> +}
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index a990a6cb184f..4c324fd398c8 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -21,6 +21,7 @@
> #include <asm/sections.h>
> #include <asm/pgtable.h>
> #include <asm/smp.h>
> +#include <asm/sbi.h>
> #include <asm/tlbflush.h>
> #include <asm/thread_info.h>
>
> @@ -70,6 +71,7 @@ void __init setup_arch(char **cmdline_p)
> swiotlb_init(1);
> #endif
>
> + riscv_sbi_init();
> #ifdef CONFIG_SMP
> setup_smp();
> #endif
> --
> 2.21.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Sincerely yours,
Mike.
Powered by blists - more mailing lists