Date:   Tue, 27 Aug 2019 08:26:10 -0000
From:   tip-bot2 for Arnaldo Carvalho de Melo <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Adrian Hunter <adrian.hunter@...el.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Arnaldo Carvalho de Melo <acme@...hat.com>,
        Ingo Molnar <mingo@...nel.org>, Borislav Petkov <bp@...en8.de>,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf cacheline: Move cacheline related routines to
 separate files

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     125009026bfc9ec929975d35344bf69d2c636e95
Gitweb:        https://git.kernel.org/tip/125009026bfc9ec929975d35344bf69d2c636e95
Author:        Arnaldo Carvalho de Melo <acme@...hat.com>
AuthorDate:    Thu, 22 Aug 2019 16:58:29 -03:00
Committer:     Arnaldo Carvalho de Melo <acme@...hat.com>
CommitterDate: Mon, 26 Aug 2019 11:58:29 -03:00

perf cacheline: Move cacheline related routines to separate files

To disentangle util/sort.h a bit more.

Cc: Adrian Hunter <adrian.hunter@...el.com>
Cc: Jiri Olsa <jolsa@...nel.org>
Cc: Namhyung Kim <namhyung@...nel.org>
Link: https://lkml.kernel.org/n/tip-6kbf2cauas06rbqp15pyter5@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 tools/perf/builtin-c2c.c    |  1 +
 tools/perf/util/Build       |  1 +
 tools/perf/util/cacheline.c | 26 ++++++++++++++++++++++++++
 tools/perf/util/cacheline.h | 21 +++++++++++++++++++++
 tools/perf/util/sort.c      |  1 +
 tools/perf/util/sort.h      | 12 ------------
 tools/perf/util/util.c      | 20 --------------------
 tools/perf/util/util.h      |  1 -
 8 files changed, 50 insertions(+), 33 deletions(-)
 create mode 100644 tools/perf/util/cacheline.c
 create mode 100644 tools/perf/util/cacheline.h

diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 2111437..73782d9 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -26,6 +26,7 @@
 #include "hist.h"
 #include "sort.h"
 #include "tool.h"
+#include "cacheline.h"
 #include "data.h"
 #include "event.h"
 #include "evlist.h"
diff --git a/tools/perf/util/Build b/tools/perf/util/Build
index b922c8c..2e38564 100644
--- a/tools/perf/util/Build
+++ b/tools/perf/util/Build
@@ -1,6 +1,7 @@
 perf-y += annotate.o
 perf-y += block-range.o
 perf-y += build-id.o
+perf-y += cacheline.o
 perf-y += config.o
 perf-y += ctype.o
 perf-y += db-export.o
diff --git a/tools/perf/util/cacheline.c b/tools/perf/util/cacheline.c
new file mode 100644
index 0000000..9361d3f
--- /dev/null
+++ b/tools/perf/util/cacheline.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "cacheline.h"
+#include "../perf.h"
+#include <unistd.h>
+
+#ifdef _SC_LEVEL1_DCACHE_LINESIZE
+#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)
+#else
+#include <api/fs/fs.h>
+#include "debug.h"
+static void cache_line_size(int *cacheline_sizep)
+{
+	if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
+		pr_debug("cannot determine cache line size");
+}
+#endif
+
+int cacheline_size(void)
+{
+	static int size;
+
+	if (!size)
+		cache_line_size(&size);
+
+	return size;
+}
diff --git a/tools/perf/util/cacheline.h b/tools/perf/util/cacheline.h
new file mode 100644
index 0000000..dec8c0f
--- /dev/null
+++ b/tools/perf/util/cacheline.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef PERF_CACHELINE_H
+#define PERF_CACHELINE_H
+
+#include <linux/compiler.h>
+
+int __pure cacheline_size(void);
+
+static inline u64 cl_address(u64 address)
+{
+	/* return the cacheline of the address */
+	return (address & ~(cacheline_size() - 1));
+}
+
+static inline u64 cl_offset(u64 address)
+{
+	/* return the cacheline of the address */
+	return (address & (cacheline_size() - 1));
+}
+
+#endif // PERF_CACHELINE_H
diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c
index f9a38a1..904ff4b 100644
--- a/tools/perf/util/sort.c
+++ b/tools/perf/util/sort.c
@@ -6,6 +6,7 @@
 #include <linux/time64.h>
 #include "sort.h"
 #include "hist.h"
+#include "cacheline.h"
 #include "comm.h"
 #include "map.h"
 #include "symbol.h"
diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h
index 5e34676..4ae155c 100644
--- a/tools/perf/util/sort.h
+++ b/tools/perf/util/sort.h
@@ -204,18 +204,6 @@ static inline float hist_entry__get_percent_limit(struct hist_entry *he)
 	return period * 100.0 / total_period;
 }
 
-static inline u64 cl_address(u64 address)
-{
-	/* return the cacheline of the address */
-	return (address & ~(cacheline_size() - 1));
-}
-
-static inline u64 cl_offset(u64 address)
-{
-	/* return the cacheline of the address */
-	return (address & (cacheline_size() - 1));
-}
-
 enum sort_mode {
 	SORT_MODE__NORMAL,
 	SORT_MODE__BRANCH,
diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c
index 6fd130a..44211e4 100644
--- a/tools/perf/util/util.c
+++ b/tools/perf/util/util.c
@@ -43,26 +43,6 @@ void perf_set_multithreaded(void)
 
 unsigned int page_size;
 
-#ifdef _SC_LEVEL1_DCACHE_LINESIZE
-#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE)
-#else
-static void cache_line_size(int *cacheline_sizep)
-{
-	if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep))
-		pr_debug("cannot determine cache line size");
-}
-#endif
-
-int cacheline_size(void)
-{
-	static int size;
-
-	if (!size)
-		cache_line_size(&size);
-
-	return size;
-}
-
 int sysctl_perf_event_max_stack = PERF_MAX_STACK_DEPTH;
 int sysctl_perf_event_max_contexts_per_stack = PERF_MAX_CONTEXTS_PER_STACK;
 
diff --git a/tools/perf/util/util.h b/tools/perf/util/util.h
index 0dab140..45a5c6f 100644
--- a/tools/perf/util/util.h
+++ b/tools/perf/util/util.h
@@ -34,7 +34,6 @@ int copyfile_offset(int ifd, loff_t off_in, int ofd, loff_t off_out, u64 size);
 size_t hex_width(u64 v);
 
 extern unsigned int page_size;
-int __pure cacheline_size(void);
 
 int sysctl__max_stack(void);
 

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