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Message-Id: <20190827.215955.401060732796152198.davem@davemloft.net>
Date: Tue, 27 Aug 2019 21:59:55 -0700 (PDT)
From: David Miller <davem@...emloft.net>
To: weifeng.voon@...el.com
Cc: mcoquelin.stm32@...il.com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, joabreu@...opsys.com,
peppe.cavallaro@...com, andrew@...n.ch, alexandre.torgue@...com,
boon.leong.ong@...el.com
Subject: Re: [PATCH v1 net-next 0/4] Add EHL and TGL PCI info and PCI ID
From: Voon Weifeng <weifeng.voon@...el.com>
Date: Tue, 27 Aug 2019 09:38:07 +0800
> In order to keep PCI info simple and neat, this patch series have
> introduced a 3 hierarchy of struct. First layer will be the
> intel_mgbe_common_data struct which keeps all Intel common configuration.
> Second layer will be xxx_common_data which keeps all the different Intel
> microarchitecture, e.g tgl, ehl. The third layer will be configuration
> that tied to the PCI ID only based on speed and RGMII/SGMII interface.
>
> EHL and TGL will also having a higher system clock which is 200Mhz.
Series applied.
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