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Message-ID: <20190828093731.GO2386@hirez.programming.kicks-ass.net>
Date: Wed, 28 Aug 2019 11:37:31 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: kan.liang@...ux.intel.com
Cc: acme@...nel.org, mingo@...hat.com, linux-kernel@...r.kernel.org,
tglx@...utronix.de, jolsa@...nel.org, eranian@...gle.com,
alexander.shishkin@...ux.intel.com, ak@...ux.intel.com
Subject: Re: [RESEND PATCH V3 2/8] perf/x86/intel: Basic support for metrics
counters
On Wed, Aug 28, 2019 at 11:02:17AM +0200, Peter Zijlstra wrote:
> @@ -2192,8 +2227,22 @@ static void intel_pmu_read_event(struct
> static void intel_pmu_enable_fixed(struct perf_event *event)
> {
> struct hw_perf_event *hwc = &event->hw;
> - int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
> u64 ctrl_val, mask, bits = 0;
> + int idx = hwc->idx;
> +
> + if (is_topdown_idx(idx)) {
> + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> + /*
> + * When there are other Top-Down events already active; don't
> + * enable the SLOTS counter.
> + */
> + if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
> + return;
> +
> + idx = INTEL_PMC_IDX_FIXED_SLOTS;
> + }
> +
> + intel_set_masks(event, hwc->idx);
That wants to be idx, not hwc->idx.
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