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Message-ID: <58b828bd-d691-f460-49aa-7e6f15180343@deltatee.com>
Date: Thu, 29 Aug 2019 17:41:52 -0600
From: Logan Gunthorpe <logang@...tatee.com>
To: Paul Walmsley <paul.walmsley@...ive.com>
Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Palmer Dabbelt <palmer@...ive.com>,
Rob Herring <robh@...nel.org>,
Albert Ou <aou@...s.berkeley.edu>,
Andrew Waterman <andrew@...ive.com>,
Mike Rapoport <rppt@...ux.ibm.com>,
Zong Li <zong@...estech.com>,
Michael Clark <michaeljclark@....com>,
Olof Johansson <olof@...om.net>,
Greentime Hu <greentime.hu@...ive.com>,
Stephen Bates <sbates@...thlin.com>,
Christoph Hellwig <hch@....de>
Subject: Re: [PATCH v6] RISC-V: Implement sparsemem
On 2019-08-29 5:38 p.m., Paul Walmsley wrote:
>> +#ifdef CONFIG_SPARSEMEM
>> +#define MAX_PHYSMEM_BITS CONFIG_PA_BITS
>> +#define SECTION_SIZE_BITS 27
>
> Do you have a specific rationale behind this selection, or is this simply
> a reasonable starting point?
It's inline with what other platforms are doing. So in some ways it's a
reasonable starting point but I don't see any reason to change it in the
near term.
>> +#endif /* CONFIG_SPARSEMEM */
>> +
>> +#endif /* __ASM_SPARSEMEM_H */
>
> The following is what I'm getting ready to queue.
Great, thanks!
Logan
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