linux-kernel - [PATCH] ASoC: fsl_sai: Set SAI Channel Mode to Output Mode

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Message-Id: <20190830225514.5283-1-daniel.baluta@nxp.com>
Date:   Sat, 31 Aug 2019 01:55:14 +0300
From:   Daniel Baluta <daniel.baluta@....com>
To:     broonie@...nel.org
Cc:     festevam@...il.com, nicoleotsuka@...il.com, Xiubo.Lee@...il.com,
        shengjiu.wang@....com, alsa-devel@...a-project.org,
        linux-kernel@...r.kernel.org, timur@...nel.org,
        gabrielcsmo@...il.com, Daniel Baluta <daniel.baluta@....com>,
        NXP Linux Team <linux-imx@....com>,
        Cosmin-Gabriel Samoila <cosmin.samoila@....com>
Subject: [PATCH] ASoC: fsl_sai: Set SAI Channel Mode to Output Mode

>From SAI datasheet:

CHMOD, configures if transmit data pins are configured for TDM mode
or Output mode.
	* (0) TDM mode, transmit data pins are tri-stated when slots are
	masked or channels are disabled.
	* (1) Output mode, transmit data pins are never tri-stated and
	will output zero when slots are masked or channels are disabled.

When data pins are tri-stated, there is noise on some channels
when FS clock value is high and data is read while fsclk is
transitioning from high to low.

Fix this by setting CHMOD to Output Mode so that pins will output zero
when slots are masked or channels are disabled.

Cc: NXP Linux Team <linux-imx@....com>
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@....com>
Signed-off-by: Daniel Baluta <daniel.baluta@....com>
---
 sound/soc/fsl/fsl_sai.c | 15 ++++++++++++---
 sound/soc/fsl/fsl_sai.h |  2 ++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index e896b577b1f7..b9daab0eb6eb 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -467,6 +467,12 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 
 	val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
 
+	/*
+	 * set CHMOD to Output Mode so that transmit data pins will
+	 * output zero when slots are masked or channels are disabled
+	 */
+	val_cr4 |= FSL_SAI_CR4_CHMOD;
+
 	/*
 	 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
 	 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
@@ -477,7 +483,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 	if (!sai->is_slave_mode) {
 		if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
 			regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
-				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
+				FSL_SAI_CR4_CHMOD_MASK,
 				val_cr4);
 			regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
 				FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
@@ -486,7 +493,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 				~0UL - ((1 << channels) - 1));
 		} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
 			regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
-				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+				FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
+				FSL_SAI_CR4_CHMOD_MASK,
 				val_cr4);
 			regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
 				FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
@@ -497,7 +505,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 	}
 
 	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
-			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
+			   FSL_SAI_CR4_CHMOD_MASK,
 			   val_cr4);
 	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
 			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index f96f8d97489d..1e3b4a6889a8 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -119,6 +119,8 @@
 #define FSL_SAI_CR4_FRSZ_MASK	(0x1f << 16)
 #define FSL_SAI_CR4_SYWD(x)	(((x) - 1) << 8)
 #define FSL_SAI_CR4_SYWD_MASK	(0x1f << 8)
+#define FSL_SAI_CR4_CHMOD	BIT(5)
+#define FSL_SAI_CR4_CHMOD_MASK	GENMASK(5, 5)
 #define FSL_SAI_CR4_MF		BIT(4)
 #define FSL_SAI_CR4_FSE		BIT(3)
 #define FSL_SAI_CR4_FSP		BIT(1)
-- 
2.17.1