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Message-ID: <BYAPR12MB2710BDF98FA472A77D106814B3BD0@BYAPR12MB2710.namprd12.prod.outlook.com>
Date: Fri, 30 Aug 2019 17:25:11 +0000
From: Krishna Reddy <vdumpa@...dia.com>
To: Robin Murphy <robin.murphy@....com>
CC: Sachin Nikam <Snikam@...dia.com>,
"Thomas Zeng (SW-TEGRA)" <thomasz@...dia.com>,
Juha Tukkinen <jtukkinen@...dia.com>,
Mikko Perttunen <mperttunen@...dia.com>,
Pritesh Raithatha <praithatha@...dia.com>,
"iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Timo Alho <talho@...dia.com>, Yu-Huan Hsu <YHsu@...dia.com>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
Thierry Reding <treding@...dia.com>,
Alexander Van Brunt <avanbrunt@...dia.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"will.deacon@....com" <will.deacon@....com>,
"joro@...tes.org" <joro@...tes.org>
Subject: RE: [PATCH 6/7] arm64: tegra: Add DT node for T194 SMMU
>> + #global-interrupts = <1>;
>Shouldn't that be 3?
Interrupt line is shared between global and all context faults for each SMMU instance.
Nvidia implementation checks for both Global and context faults on each interrupt to an SMMU instance.
It can be either 1 or 3. If we make it 3, we need to add two more irq entries in node for context faults.
In the future, we can update arm-smmu.c to support shared interrupt line between global and all context faults.
-KR
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