| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <1567413310-2589-1-git-send-email-weiyi.lu@mediatek.com>
Date: Mon, 2 Sep 2019 16:35:07 +0800
From: Weiyi Lu <weiyi.lu@...iatek.com>
To: Nicolas Boichat <drinkcat@...omium.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Rob Herring <robh@...nel.org>
CC: James Liao <jamesjj.liao@...iatek.com>,
Fan Chen <fan.chen@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<srv_heupstream@...iatek.com>, CK Hu <ck.hu@...iatek.com>,
Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [PATCH v1 0/3] Runtime PM support for MT8183 mcucfg clock provider
This series is based on v5.3-rc1 and Mediatek MT8183 scpsys support v7[1].
Since Runtime PM is supported in Common Clock Framework which keeps
clock controller's power domain enabled to ensure clock status accessing correctly.
[1] https://patchwork.kernel.org/cover/11118371/
---
Weiyi Lu (3):
clk: mediatek: Register clock gate with device
clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
arm64: dts: Add power-domains properity to mfgcfg
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h | 3 ++-
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 7 +++++--
drivers/clk/mediatek/clk-mtk.c | 16 +++++++++++++---
drivers/clk/mediatek/clk-mtk.h | 5 +++++
6 files changed, 29 insertions(+), 8 deletions(-)
Powered by blists - more mailing lists