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Message-ID: <1567414859-3244-4-git-send-email-weiyi.lu@mediatek.com>
Date: Mon, 2 Sep 2019 17:00:59 +0800
From: Weiyi Lu <weiyi.lu@...iatek.com>
To: Nicolas Boichat <drinkcat@...omium.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>
CC: James Liao <jamesjj.liao@...iatek.com>,
Fan Chen <fan.chen@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<srv_heupstream@...iatek.com>, CK Hu <ck.hu@...iatek.com>,
Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [RESEND PATCH v1 3/3] arm64: dts: Add power-domains properity to mfgcfg
mfgcfg clock is under MFG_ASYNC power domain
Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4..3f948e9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -388,6 +388,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
mmsys: syscon@...00000 {
--
1.8.1.1.dirty
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