linux-kernel - Re: [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards

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Message-ID: <CAL_Jsq+VmFi6r1-WOa9RJ4vfqsZLqcn5HMbv1oyQjhtJ8Qd8Lw@mail.gmail.com>
Date:   Mon, 2 Sep 2019 15:50:47 +0100
From:   Rob Herring <robh+dt@...nel.org>
To:     Paul Burton <paul.burton@...s.com>
Cc:     Jiaxun Yang <jiaxun.yang@...goat.com>,
        "open list:MIPS" <linux-mips@...r.kernel.org>,
        Huacai Chen <chenhc@...ote.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <maz@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Mark Rutland <mark.rutland@....co>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards

On Tue, Aug 27, 2019 at 9:41 PM Paul Burton <paul.burton@...s.com> wrote:
>
> Hi guys,
>
> On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote:
> > On 2019/8/27 下午8:45, Rob Herring wrote:
> > > On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@...goat.com> wrote:
> > > > diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> > > > new file mode 100644
> > > > index 000000000000..410d896a0078
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml
> > > > @@ -0,0 +1,38 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > Dual license for new bindings please:
> > >
> > > (GPL-2.0-only OR BSD-2-Clause)
> > >
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Loongson CPUs bindings
> > > > +
> > > > +maintainers:
> > > > +  - Jiaxun Yang <jiaxun.yang@...goat.com>
> > > > +
> > > > +description: |+
> > > > +  The device tree allows to describe the layout of CPUs in a system through
> > > > +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > > > +  defining properties for every cpu.
> > > > +
> > > > +  Bindings for CPU nodes follow the Devicetree Specification, available from:
> > > > +
> > > > +  https://www.devicetree.org/specifications/
> > > > +
> > > > +properties:
> > > > +  reg:
> > > > +    maxItems: 1
> > > > +    description: |
> > > > +      Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
> > > Is this definition specific to Loongson CPUs or all MIPS?
> >
> > Currently it's specific to Loongson CPU only, as other processors may using
> > different method to express CPU map.
> >
> > Different from Arm, MIPS family of processors seems less uniform and have
> > their own designs.
> >
> > For this point, we'd better ask Paul's opinion.
>
> In general on MIPS we detect CPU properties at runtime from coprocessor
> 0 registers & similar sources of information, so there's not really a
> need to specify anything about the CPU in devicetree.

We thought the same thing initially for Arm... Mostly what is in DT is
not what is discoverable. Are clock speeds, power domains, low power
states, etc. all discoverable?

> For example here
> you say yourself that the value for this property can be read from
> EBase.CPUNum - so why specify it in DT?

To map DT nodes to cores?

Rob