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Date: Tue, 3 Sep 2019 12:21:51 +0530
From: Pragnesh Patel <pragnesh.patel@...ive.com>
To: Rob Herring <robh@...nel.org>
Cc: Palmer Dabbelt <palmer@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Mark Rutland <mark.rutland@....com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: serial: Convert riscv,sifive-serial to json-schema
On Mon, Sep 2, 2019 at 7:09 PM Rob Herring <robh@...nel.org> wrote:
>
> On Sun, Sep 01, 2019 at 12:39:21PM +0530, Pragnesh Patel wrote:
> > Convert the riscv,sifive-serial binding to DT schema using json-schema.
> >
> > Signed-off-by: Pragnesh Patel <pragnesh.patel@...ive.com>
> > ---
> > .../devicetree/bindings/serial/sifive-serial.txt | 33 ------------
> > .../devicetree/bindings/serial/sifive-serial.yaml | 62 ++++++++++++++++++++++
> > 2 files changed, 62 insertions(+), 33 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/serial/sifive-serial.txt
> > create mode 100644 Documentation/devicetree/bindings/serial/sifive-serial.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.txt b/Documentation/devicetree/bindings/serial/sifive-serial.txt
> > deleted file mode 100644
> > index c86b1e5..0000000
> > --- a/Documentation/devicetree/bindings/serial/sifive-serial.txt
> > +++ /dev/null
> > @@ -1,33 +0,0 @@
> > -SiFive asynchronous serial interface (UART)
> > -
> > -Required properties:
> > -
> > -- compatible: should be something similar to
> > - "sifive,<chip>-uart" for the UART as integrated
> > - on a particular chip, and "sifive,uart<version>" for the
> > - general UART IP block programming model. Supported
> > - compatible strings as of the date of this writing are:
> > - "sifive,fu540-c000-uart" for the SiFive UART v0 as
> > - integrated onto the SiFive FU540 chip, or "sifive,uart0"
> > - for the SiFive UART v0 IP block with no chip integration
> > - tweaks (if any)
> > -- reg: address and length of the register space
> > -- interrupts: Should contain the UART interrupt identifier
> > -- clocks: Should contain a clock identifier for the UART's parent clock
> > -
> > -
> > -UART HDL that corresponds to the IP block version numbers can be found
> > -here:
> > -
> > -https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
> > -
> > -
> > -Example:
> > -
> > -uart0: serial@...10000 {
> > - compatible = "sifive,fu540-c000-uart", "sifive,uart0";
> > - interrupt-parent = <&plic0>;
> > - interrupts = <80>;
> > - reg = <0x0 0x10010000 0x0 0x1000>;
> > - clocks = <&prci PRCI_CLK_TLCLK>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
> > new file mode 100644
> > index 0000000..56fa935
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive asynchronous serial interface (UART)
> > +
> > +maintainers:
> > + - Pragnesh Patel <pragnesh.patel@...ive.com>
> > + - Paul Walmsley <paul.walmsley@...ive.com>
> > + - Palmer Dabbelt <palmer@...ive.com>
> > +
> > +allOf:
> > + - $ref: /schemas/serial.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - sifive,fu540-c000-uart
> > + - sifive,uart0
>
> This is wrong and should have warned if you tested this on 5.3.
>
> items:
> - const: sifive,fu540-c000-uart
> - const: sifive,uart0
>
Thanks for the correction, i will update this in v2 patch.
I haven't got any warnings due to my patch.
For your reference, following is the list of warnings when i did "make
dtbs_check" (kernel version - 5.3.0-rc7)
/home/pragneshp/opensource/linux/Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0',
'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
/home/pragneshp/opensource/linux/Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0: compatible: ['riscv'] is too short
/home/pragneshp/opensource/linux/Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@0: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml:
cpu@1: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
/: compatible: ['sifive,hifive-unleashed-a00', 'sifive,fu540-c000'] is
too short
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@3: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@3: compatible: Additional items are not allowed ('riscv' was
unexpected)
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@3: compatible:1: 'riscv' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@3: compatible: ['sifive,u54-mc', 'sifive,rocket0', 'riscv'] is too
long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@1: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@1: compatible: Additional items are not allowed ('riscv' was
unexpected)
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@1: compatible:1: 'riscv' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@1: compatible: ['sifive,u54-mc', 'sifive,rocket0', 'riscv'] is too
long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@4: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@4: compatible: Additional items are not allowed ('riscv' was
unexpected)
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@4: compatible:1: 'riscv' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@4: compatible: ['sifive,u54-mc', 'sifive,rocket0', 'riscv'] is too
long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@2: 'timebase-frequency' is a required property
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@2: compatible: Additional items are not allowed ('riscv' was
unexpected)
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@2: compatible:1: 'riscv' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@2: compatible: ['sifive,u54-mc', 'sifive,rocket0', 'riscv'] is too
long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@0: compatible: Additional items are not allowed ('riscv' was
unexpected)
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@0: compatible:1: 'riscv' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
cpu@0: compatible: ['sifive,e51', 'sifive,rocket0', 'riscv'] is too
long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: compatible:0: 'sifive,fu540-c000' is not one of
['sifive,hifive-unleashed-a00']
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: compatible:1: 'sifive,fu540-c000' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: compatible:2: 'sifive,fu540' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: $nodename:0: '/' was expected
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: spi@...41000:reg:0: [0, 268701696, 0, 4096, 0, 805306368, 0,
268435456] is too long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: ethernet@...90000:reg:0: [0, 269025280, 0, 8192, 0, 269090816, 0,
4096] is too long
/home/pragneshp/opensource/linux/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml:
soc: spi@...40000:reg:0: [0, 268697600, 0, 4096, 0, 536870912, 0,
268435456] is too long
>
> > +
> > + description:
> > + Should be something similar to "sifive,<chip>-uart"
> > + for the UART as integrated on a particular chip,
> > + and "sifive,uart<version>" for the general UART IP
> > + block programming model.
> > +
> > + UART HDL that corresponds to the IP block version
> > + numbers can be found here -
> > +
> > + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/sifive-fu540-prci.h>
> > + serial@...10000 {
> > + compatible = "sifive,fu540-c000-uart", "sifive,uart0";
> > + interrupt-parent = <&plic0>;
> > + interrupts = <80>;
> > + reg = <0x0 0x10010000 0x0 0x1000>;
> > + clocks = <&prci PRCI_CLK_TLCLK>;
> > + };
> > +
> > +...
> > --
> > 2.7.4
> >
>
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