linux-kernel - [PATCH v2 4/4] drm/ttm: Cache dma pool decrypted pages when AMD SEV is active

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Date:   Tue,  3 Sep 2019 15:15:04 +0200
From:   Thomas Hellström (VMware) 
        <thomas_os@...pmail.org>
To:     dri-devel@...ts.freedesktop.org, pv-drivers@...are.com,
        linux-graphics-maintainer@...are.com, linux-kernel@...r.kernel.org
Cc:     Thomas Hellstrom <thellstrom@...are.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Andy Lutomirski <luto@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        Heiko Carstens <heiko.carstens@...ibm.com>,
        Christian Borntraeger <borntraeger@...ibm.com>,
        Tom Lendacky <thomas.lendacky@....com>,
        Christian König <christian.koenig@....com>
Subject: [PATCH v2 4/4] drm/ttm: Cache dma pool decrypted pages when AMD SEV is active

From: Thomas Hellstrom <thellstrom@...are.com>

The TTM dma pool allocates coherent pages for use with TTM. When forcing
unencrypted DMA, such allocations become very expensive since the linear
kernel map has to be changed to mark the pages decrypted. To avoid too many
such allocations and frees, cache the decrypted pages even if they
are in the normal cpu caching state, where otherwise the pool frees them
immediately when unused.

Tested with vmwgfx on SEV-ES.

Cc: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Ingo Molnar <mingo@...hat.com>
Cc: Borislav Petkov <bp@...en8.de>
Cc: "H. Peter Anvin" <hpa@...or.com>
Cc: Heiko Carstens <heiko.carstens@...ibm.com>
Cc: Christian Borntraeger <borntraeger@...ibm.com>
Cc: Tom Lendacky <thomas.lendacky@....com>
Cc: Christian König <christian.koenig@....com>
Signed-off-by: Thomas Hellstrom <thellstrom@...are.com>
---
 drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 9b15df8ecd49..a3247f24e106 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -1000,7 +1000,7 @@ void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev)
 	struct dma_pool *pool;
 	struct dma_page *d_page, *next;
 	enum pool_type type;
-	bool is_cached = false;
+	bool immediate_free = false;
 	unsigned count, i, npages = 0;
 	unsigned long irq_flags;
 
@@ -1035,8 +1035,17 @@ void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev)
 	if (!pool)
 		return;
 
-	is_cached = (ttm_dma_find_pool(pool->dev,
-		     ttm_to_type(ttm->page_flags, tt_cached)) == pool);
+	/*
+	 * If memory is cached and sev encryption is not active, allocating
+	 * and freeing coherent memory is relatively cheap, so we can free
+	 * it immediately. If sev encryption is active, allocating coherent
+	 * memory involves a call to set_memory_decrypted() which is very
+	 * expensive, so cache coherent pages is sev is active.
+	 */
+	immediate_free = (ttm_dma_find_pool
+			  (pool->dev,
+			   ttm_to_type(ttm->page_flags, tt_cached)) == pool &&
+			  !force_dma_unencrypted(dev));
 
 	/* make sure pages array match list and count number of pages */
 	count = 0;
@@ -1051,13 +1060,13 @@ void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev)
 			d_page->vaddr &= ~VADDR_FLAG_UPDATED_COUNT;
 		}
 
-		if (is_cached)
+		if (immediate_free)
 			ttm_dma_page_put(pool, d_page);
 	}
 
 	spin_lock_irqsave(&pool->lock, irq_flags);
 	pool->npages_in_use -= count;
-	if (is_cached) {
+	if (immediate_free) {
 		pool->nfrees += count;
 	} else {
 		pool->npages_free += count;
-- 
2.20.1