linux-kernel - Re: [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform

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Message-ID: <287e3013-9011-79f8-fc1d-56184480cdb7@nvidia.com>
Date:   Thu, 5 Sep 2019 16:20:31 +0530
From:   Vidya Sagar <vidyas@...dia.com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC:     <bhelgaas@...gle.com>, <robh+dt@...nel.org>,
        <thierry.reding@...il.com>, <jonathanh@...dia.com>,
        <andrew.murray@....com>, <kishon@...com>,
        <gustavo.pimentel@...opsys.com>, <digetx@...il.com>,
        <mperttunen@...dia.com>, <linux-pci@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <kthota@...dia.com>,
        <mmaddireddy@...dia.com>, <sagar.tv@...il.com>
Subject: Re: [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194
 in p2972-0000 platform

On 9/5/2019 3:04 PM, Lorenzo Pieralisi wrote:
> On Thu, Sep 05, 2019 at 01:44:46PM +0530, Vidya Sagar wrote:
>> Hi Lorenzo / Bjorn,
>> Can you please review this series?
>> I have Reviewed-by and Acked-by from Rob, Thierry and Andrew already.
> 
> Rebase it on top of my pci/tegra branch (it does not apply),
> resend it and I will merge it.
I just sent V4 after rebasing the series on top of pci/tegra.

Thanks,
Vidya Sagar
> 
> Thanks,
> Lorenzo
> 
>> Thanks,
>> Vidya Sagar
>>
>> On 8/28/2019 10:58 PM, Vidya Sagar wrote:
>>> This patch series enables Tegra194's C5 controller which owns x16 slot in
>>> p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as
>>> output and bi-directional signals by default and hence they need to be
>>> configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled
>>> through GPIOs and hence they need to be enabled through regulator framework.
>>> This patch series adds required infrastructural support to address both the
>>> aforementioned requirements.
>>> Testing done on p2972-0000 platform
>>> - Able to enumerate devices connected to x16 slot (owned by C5 controller)
>>> - Enumerated device's functionality verified
>>> - Suspend-Resume sequence is verified with device connected to x16 slot
>>>
>>> V3:
>>> * Addressed some more review comments from Andrew Murray and Thierry Reding
>>>
>>> V2:
>>> * Changed the order of patches in the series for easy merging
>>> * Addressed review comments from Thierry Reding and Andrew Murray
>>>
>>> Vidya Sagar (6):
>>>     dt-bindings: PCI: tegra: Add sideband pins configuration entries
>>>     dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
>>>     PCI: tegra: Add support to configure sideband pins
>>>     PCI: tegra: Add support to enable slot regulators
>>>     arm64: tegra: Add configuration for PCIe C5 sideband signals
>>>     arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
>>>
>>>    .../bindings/pci/nvidia,tegra194-pcie.txt     | 16 ++++
>>>    .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++
>>>    .../boot/dts/nvidia/tegra194-p2972-0000.dts   |  4 +-
>>>    arch/arm64/boot/dts/nvidia/tegra194.dtsi      | 38 +++++++-
>>>    drivers/pci/controller/dwc/pcie-tegra194.c    | 94 ++++++++++++++++++-
>>>    5 files changed, 172 insertions(+), 4 deletions(-)
>>>
>>