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Message-ID: <20190906174815.GZ2680@smile.fi.intel.com>
Date: Fri, 6 Sep 2019 20:48:15 +0300
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Ivan Gorinov <ivan.gorinov@...el.com>
Cc: "Chuan Hua, Lei" <chuanhua.lei@...ux.intel.com>,
Dilip Kota <eswara.kota@...ux.intel.com>, jingoohan1@...il.com,
gustavo.pimentel@...opsys.com, lorenzo.pieralisi@....com,
robh@...nel.org, linux-pci@...r.kernel.org, hch@...radead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
cheol.yong.kim@...el.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v3 1/2] dt-bindings: PCI: intel: Add YAML schemas for the
PCIe RC controller
On Fri, Sep 06, 2019 at 07:17:11PM +0200, Martin Blumenstingl wrote:
> On Fri, Sep 6, 2019 at 5:22 AM Chuan Hua, Lei
> <chuanhua.lei@...ux.intel.com> wrote:
> > type_index = fwspec->param[1]; // index.
> > if (type_index >= ARRAY_SIZE(of_ioapic_type))
> > return -EINVAL;
> >
> > I would not see this definition is user-friendly. But it is how x86
> > handles at the moment.
> thank you for explaining this - I had no idea x86 is different from
> all other platforms I know
> the only upstream x86 .dts I could find
> (arch/x86/platform/ce4100/falconfalls.dts) also uses the magic x86
> numbers
> so I'm fine with this until someone else knows a better solution
Ivan, Cc'ed, had done few amendments to x86 DT support. Perhaps he may add
something to the discussion.
--
With Best Regards,
Andy Shevchenko
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