linux-kernel - Re: [PATCH v5 2/7] PCI: Add ACS quirk for Amazon Annapurna Labs root ports

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Date:   Sat, 7 Sep 2019 11:54:50 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Jonathan Chocron <jonnyc@...zon.com>
Cc:     lorenzo.pieralisi@....com, jingoohan1@...il.com,
        gustavo.pimentel@...opsys.com, robh+dt@...nel.org,
        mark.rutland@....com, andrew.murray@....com, dwmw@...zon.co.uk,
        benh@...nel.crashing.org, alisaidi@...zon.com, ronenk@...zon.com,
        barakw@...zon.com, talel@...zon.com, hanochu@...zon.com,
        hhhawa@...zon.com, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v5 2/7] PCI: Add ACS quirk for Amazon Annapurna Labs root
 ports

On Thu, Sep 05, 2019 at 05:00:16PM +0300, Jonathan Chocron wrote:
> From: Ali Saidi <alisaidi@...zon.com>
> 
> The Amazon's Annapurna Labs root ports don't advertise an ACS
> capability, but they don't allow peer-to-peer transactions and do
> validate bus numbers through the SMMU. Additionally, it's not possible
> for one RP to pass traffic to another RP.
> 
> Signed-off-by: Ali Saidi <alisaidi@...zon.com>
> Signed-off-by: Jonathan Chocron <jonnyc@...zon.com>
> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@...opsys.com>
> Reviewed-by: Andrew Murray <andrew.murray@....com>

Acked-by: Bjorn Helgaas <bhelgaas@...gle.com>

But please tweak it as below ...

> ---
>  drivers/pci/quirks.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index ded60757a573..8fe765592943 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -4418,6 +4418,24 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
>  	return ret;
>  }
>  
> +static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
> +{
> +	/*
> +	 * Amazon's Annapurna Labs root ports don't include an ACS capability,
> +	 * but do include ACS-like functionality. The hardware doesn't support
> +	 * peer-to-peer transactions via the root port and each has a unique
> +	 * segment number.
> +	 *
> +	 * Additionally, the root ports cannot send traffic to each other.
> +	 */
> +	acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);

There are several quirks that use this same set of bits, but they
don't use the same order, which is a needless difference.

Can you reorder them in the bit 0 ... bit 7 order?  I.e.,

    PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF

> +	if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
> +		return -ENOTTY;

This could go first (above the comment) so all the acs_flags stuff is
together.

> +	return acs_flags ? 0 : 1;
> +}
> +
>  /*
>   * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
>   * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
> @@ -4611,6 +4629,8 @@ static const struct pci_dev_acs_enabled {
>  	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
>  	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
>  	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
> +	/* Amazon Annapurna Labs */
> +	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
>  	{ 0 }
>  };
>  
> -- 
> 2.17.1
>