linux-kernel - Re: [PATCH v2 3/4] x86/mce: Add Zhaoxin CMCI support

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Date:   Tue, 10 Sep 2019 14:37:20 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Tony W Wang-oc <TonyWWang-oc@...oxin.com>
Cc:     "tony.luck@...el.com" <tony.luck@...el.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "yazen.ghannam@....com" <yazen.ghannam@....com>,
        "vishal.l.verma@...el.com" <vishal.l.verma@...el.com>,
        "qiuxu.zhuo@...el.com" <qiuxu.zhuo@...el.com>,
        David Wang <DavidWang@...oxin.com>,
        "Cooper Yan(BJ-RD)" <CooperYan@...oxin.com>,
        "Qiyuan Wang(BJ-RD)" <QiyuanWang@...oxin.com>,
        "Herry Yang(BJ-RD)" <HerryYang@...oxin.com>
Subject: Re: [PATCH v2 3/4] x86/mce: Add Zhaoxin CMCI support

On Tue, Sep 10, 2019 at 08:19:44AM +0000, Tony W Wang-oc wrote:
> @@ -1777,6 +1777,29 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
>  	}
>  }
>
> +#ifdef CONFIG_CPU_SUP_ZHAOXIN

What's that ifdeffery for since you have it in the header already?

> +void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
> +{
> +	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
> +
> +	/*
> +	 * These CPUs bank8 SVAD error may be triggered unexpected when

"These CPUs bank8 SVAD"??

> +	 * bringup virtual machine. it is not hardware bug. Always disable
> +	 * bank8 SVAD error by default.
> +	 */

That comment is incomprehensible. Please rewrite.

> +	if ((c->x86 == 6 && c->x86_model == 0x19 &&
> +		(c->x86_stepping > 3 && c->x86_stepping < 8)) ||
> +	    (c->x86 == 6 && c->x86_model == 0x1f) ||
> +	    (c->x86 == 7 && c->x86_model == 0x1b)) {

As before: potential to simplify the test here?

> +		if (this_cpu_read(mce_num_banks) > 8)
> +			mce_banks[8].ctl = 0;
> +	}
> +
> +	intel_init_cmci();
> +	mce_adjust_timer = cmci_intel_adjust_timer;
> +}
> +#endif
> +
>  static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
>  {
>  	switch (c->x86_vendor) {
> @@ -1798,6 +1821,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
>  		mce_centaur_feature_init(c);
>  		break;
>  
> +	case X86_VENDOR_ZHAOXIN:
> +		mce_zhaoxin_feature_init(c);
> +		break;
> +
>  	default:
>  		break;
>  	}
> diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
> index eee4b12..b49cba7 100644
> --- a/arch/x86/kernel/cpu/mce/intel.c
> +++ b/arch/x86/kernel/cpu/mce/intel.c
> @@ -85,7 +85,8 @@ static int cmci_supported(int *banks)
>  	 * initialization is vendor keyed and this
>  	 * makes sure none of the backdoors are entered otherwise.
>  	 */

That comment above needs fixing too.

> -	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
> +	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
> +	    boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
>  		return 0;

<---- newline here.

>  	if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
>  		return 0;
> -- 
> 2.7.4

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette