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Date:   Thu, 12 Sep 2019 15:01:16 +0800
From:   Dilip Kota <eswara.kota@...ux.intel.com>
To:     Andy Shevchenko <andriy.shevchenko@...el.com>,
        Andrew Murray <andrew.murray@....com>
Cc:     jingoohan1@...il.com, gustavo.pimentel@...opsys.com,
        lorenzo.pieralisi@....com, robh@...nel.org,
        martin.blumenstingl@...glemail.com, linux-pci@...r.kernel.org,
        hch@...radead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
        chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH v3 2/2] dwc: PCI: intel: Intel PCIe RC controller driver

Hi Andy,

On 9/5/2019 7:40 PM, Andy Shevchenko wrote:
> On Thu, Sep 05, 2019 at 11:45:18AM +0100, Andrew Murray wrote:
>> On Wed, Sep 04, 2019 at 06:10:31PM +0800, Dilip Kota wrote:
>>> Add support to PCIe RC controller on Intel Universal
>>> Gateway SoC. PCIe controller is based of Synopsys
>>> Designware pci core.
>>> +config PCIE_INTEL_AXI
> I think that name here is too generic. Classical x86 seems not using this.

This PCIe driver is for the Intel Gateway SoCs. So how about naming it is as
"pcie-intel-gw"; pcie-intel-gw.c and Kconfig as PCIE_INTEL_GW.

Andrew Murray is ok with this naming, please let me know your view.

>
>>> +        bool "Intel AHB/AXI PCIe host controller support"
>>> +        depends on PCI_MSI
>>> +        depends on PCI
>>> +        depends on OF
>>> +        select PCIE_DW_HOST
>>> +        help
>>> +          Say 'Y' here to enable support for Intel AHB/AXI PCIe Host
>>> +	  controller driver.
>>> +	  The Intel PCIe controller is based on the Synopsys Designware
>>> +	  pcie core and therefore uses the Designware core functions to
>>> +	  implement the driver.

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