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Message-ID: <20190913181031.GA9940@agluck-desk2.amr.corp.intel.com>
Date: Fri, 13 Sep 2019 11:10:31 -0700
From: "Luck, Tony" <tony.luck@...el.com>
To: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
Cc: "Borislav Petkov (bp@...en8.de)" <bp@...en8.de>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"yazen.ghannam@....com" <yazen.ghannam@....com>,
"vishal.l.verma@...el.com" <vishal.l.verma@...el.com>,
"qiuxu.zhuo@...el.com" <qiuxu.zhuo@...el.com>,
David Wang <DavidWang@...oxin.com>,
"Cooper Yan(BJ-RD)" <CooperYan@...oxin.com>,
"Qiyuan Wang(BJ-RD)" <QiyuanWang@...oxin.com>,
"Herry Yang(BJ-RD)" <HerryYang@...oxin.com>
Subject: Re: [PATCH v3 1/4] x86/mce: Add Zhaoxin MCE support
On Wed, Sep 11, 2019 at 12:01:42PM +0000, Tony W Wang-oc wrote:
> + /* Checks after this one are Intel/Zhaoxin-specific: */
> + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
> + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
Is it time to have a big cleanup on how we handle similarities
and oddities in the MCE subsystem? We've been adding ad-hoc
tests like this in random places ... and it all looks very
messy. Lines that mention x86_vendor|x86|x86_model below
arch/x86/kernel/cpu/mce/ currently look like this:
arch/x86/kernel/cpu/mce/amd.c: (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
arch/x86/kernel/cpu/mce/amd.c: c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
arch/x86/kernel/cpu/mce/amd.c: } else if (c->x86 == 0x17 &&
arch/x86/kernel/cpu/mce/amd.c: if (c->x86 == 0x15 && bank == 4) {
arch/x86/kernel/cpu/mce/amd.c: if (c->x86 == 0x17 &&
arch/x86/kernel/cpu/mce/core.c: boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
arch/x86/kernel/cpu/mce/core.c: boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
arch/x86/kernel/cpu/mce/core.c: c->x86 > 6) {
arch/x86/kernel/cpu/mce/core.c: if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
arch/x86/kernel/cpu/mce/core.c: if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
arch/x86/kernel/cpu/mce/core.c: if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
arch/x86/kernel/cpu/mce/core.c: if (c->x86 < 0x11 && cfg->bootlog < 0) {
arch/x86/kernel/cpu/mce/core.c: if (c->x86 == 0x15 && c->x86_model <= 0xf)
arch/x86/kernel/cpu/mce/core.c: if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
arch/x86/kernel/cpu/mce/core.c: if (c->x86 != 5)
arch/x86/kernel/cpu/mce/core.c: if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
arch/x86/kernel/cpu/mce/core.c: if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
arch/x86/kernel/cpu/mce/core.c: if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
arch/x86/kernel/cpu/mce/core.c: if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
arch/x86/kernel/cpu/mce/core.c: if (c->x86 == 6 && c->x86_model == 45)
arch/x86/kernel/cpu/mce/core.c: if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
arch/x86/kernel/cpu/mce/core.c: if (c->x86_vendor == X86_VENDOR_AMD) {
arch/x86/kernel/cpu/mce/core.c: if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
arch/x86/kernel/cpu/mce/core.c: if (c->x86_vendor == X86_VENDOR_INTEL) {
arch/x86/kernel/cpu/mce/core.c: if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
arch/x86/kernel/cpu/mce/core.c: m->cpuvendor = boot_cpu_data.x86_vendor;
arch/x86/kernel/cpu/mce/core.c: switch (c->x86_vendor) {
arch/x86/kernel/cpu/mce/inject.c: boot_cpu_data.x86 < 0x17) {
arch/x86/kernel/cpu/mce/inject.c: m->cpuvendor = boot_cpu_data.x86_vendor;
arch/x86/kernel/cpu/mce/intel.c: if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
arch/x86/kernel/cpu/mce/intel.c: switch (c->x86_model) {
arch/x86/kernel/cpu/mce/severity.c: boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
arch/x86/kernel/cpu/mce/severity.c: if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
arch/x86/kernel/cpu/mce/therm_throt.c: if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
Maybe we can X86_VENDOR_ZHAOXIN to this jumble with the excuse that
it is already so ugly that this patch series only makes things 5% worse?
Or should we make a big table of CPU vendors/families/models and use
x86_match_cpu() to pick out what are running on and set some bits/flags
(like X86_FEATURE/X86_BUG) which we can use in the code to do the
right thing in each place?
E.g. default for Intel and Zhaoxin vendors would be to set MCE_INTEL_LIKE.
Thoughts?
-Tony
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