linux-kernel - Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file

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Message-ID: <mhng-166dcd4f-9483-4aab-a83a-914d70ddb5a4@palmer-si-x1e>
Date:   Sat, 14 Sep 2019 07:01:29 -0700 (PDT)
From:   Palmer Dabbelt <palmer@...ive.com>
To:     will@...nel.org
CC:     guoren@...nel.org, Will Deacon <will.deacon@....com>,
        julien.thierry@....com, aou@...s.berkeley.edu, james.morse@....com,
        Arnd Bergmann <arnd@...db.de>, suzuki.poulose@....com,
        marc.zyngier@....com, catalin.marinas@....com,
        Anup Patel <Anup.Patel@....com>, linux-kernel@...r.kernel.org,
        rppt@...ux.ibm.com, Christoph Hellwig <hch@...radead.org>,
        Atish Patra <Atish.Patra@....com>, julien.grall@....com,
        gary@...yguo.net, Paul Walmsley <paul.walmsley@...ive.com>,
        christoffer.dall@....com, linux-riscv@...ts.infradead.org,
        kvmarm@...ts.cs.columbia.edu, linux-arm-kernel@...ts.infradead.org,
        iommu@...ts.linux-foundation.org
Subject:     Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file

On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@...nel.org wrote:
> On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote:
>> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon <will@...nel.org> wrote:
>> > > I'll keep my system use the same ASID for SMP + IOMMU :P
>> >
>> > You will want a separate allocator for that:
>> >
>> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.brucker@arm.com
>>
>> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or different
>> system, because it's difficult to synchronize the IO_ASID when the CPU
>> ASID is rollover.
>> But we could still use hardware broadcast TLB invalidation instruction
>> to uniformly manage the ASID and IO_ASID, or OTHER_ASID in our IOMMU.
>
> That's probably a bad idea, because you'll likely stall execution on the
> CPU until the IOTLB has completed invalidation. In the case of ATS, I think
> an endpoint ATC is permitted to take over a minute to respond. In reality, I
> suspect the worst you'll ever see would be in the msec range, but that's
> still an unacceptable period of time to hold a CPU.
>
>> Welcome to join our disscusion:
>> "Introduce an implementation of IOMMU in linux-riscv"
>> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC
>
> I attended this session, but it unfortunately raised many more questions
> than it answered.

Ya, we're a long way from figuring this out.