linux-kernel - linux-next: manual merge of the jc_docs tree with the riscv-fixes tree

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Message-ID: <20190915194818.GC4352@sirena.co.uk>
Date:   Sun, 15 Sep 2019 20:48:18 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Jonathan Corbet <corbet@....net>,
        Mauro Carvalho Chehab <mchehab+samsung@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>
Cc:     linux-riscv@...ts.infradead.org,
        Linux Next Mailing List <linux-next@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: linux-next: manual merge of the jc_docs tree with the riscv-fixes
 tree

Hi all,

Today's linux-next merge of the jc_docs tree got a conflict in:

  Documentation/riscv/boot-image-header.rst

between commit:

  474efecb65dceb15f ("riscv: modify the Image header to improve compatibility with the ARM64 header")

from the riscv tree and commit:

  638b642f82bb8ee81 ("docs: riscv: convert boot-image-header.txt to ReST")

from the jc_docs tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc Documentation/riscv/boot-image-header.rst
index 14b1492f689bb,43e9bd0731d5f..0000000000000
--- a/Documentation/riscv/boot-image-header.rst
+++ b/Documentation/riscv/boot-image-header.rst
@@@ -15,10 -18,10 +18,10 @@@ The following 64-byte header is presen
  	u64 image_size;		  /* Effective Image size, little endian */
  	u64 flags;		  /* kernel flags, little endian */
  	u32 version;		  /* Version of this header */
- 	u32 res1  = 0;		  /* Reserved */
- 	u64 res2  = 0;    	  /* Reserved */
+ 	u32 res1 = 0;		  /* Reserved */
+ 	u64 res2 = 0;		  /* Reserved */
  	u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
 -	u32 res3;		  /* Reserved for additional RISC-V specific header */
 +	u32 magic2 = 0x56534905;  /* Magic number 2, little endian, "RSC\x05" */
  	u32 res4;		  /* Reserved for PE COFF offset */
  
  This header format is compliant with PE/COFF header and largely inspired from
@@@ -32,20 -37,25 +37,26 @@@ Note
    code0 should be replaced with "MZ" magic string and res5(at offset 0x3c) should
    point to the rest of the PE/COFF header.
  
- - version field indicate header version number.
- 	Bits 0:15  - Minor version
- 	Bits 16:31 - Major version
+ - version field indicate header version number
+ 
+ 	==========  =============
+ 	Bits 0:15   Minor version
+ 	Bits 16:31  Major version
+ 	==========  =============
  
    This preserves compatibility across newer and older version of the header.
 -  The current version is defined as 0.1.
 +  The current version is defined as 0.2.
  
 -- res3 is reserved for offset to any other additional fields. This makes the
 -  header extendible in future. One example would be to accommodate ISA
 -  extension for RISC-V in future. For current version, it is set to be zero.
 +- The "magic" field is deprecated as of version 0.2.  In a future
 +  release, it may be removed.  This originally should have matched up
 +  with the ARM64 header "magic" field, but unfortunately does not.
 +  The "magic2" field replaces it, matching up with the ARM64 header.
  
 -- In current header, the flag field has only one field.
 +- In current header, the flags field has only one field.
- 	Bit 0: Kernel endianness. 1 if BE, 0 if LE.
+ 
+ 	=====  ====================================
+ 	Bit 0  Kernel endianness. 1 if BE, 0 if LE.
+ 	=====  ====================================
  
  - Image size is mandatory for boot loader to load kernel image. Booting will
    fail otherwise.

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