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Message-ID: <32ab6570-c3b7-4eec-7a0b-69bc2f7f76dc@fortanix.com>
Date: Sun, 15 Sep 2019 20:41:55 +0000
From: Jethro Beekman <jethro@...tanix.com>
To: Marek Vasut <marek.vasut@...il.com>,
Tudor Ambarus <tudor.ambarus@...rochip.com>,
David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Mika Westerberg <mika.westerberg@...ux.intel.com>
CC: Jethro Beekman <jethro@...tanix.com>
Subject: Re: [PATCH v2 1/2] mtd: spi-nor: intel-spi: support chips without
software sequencer
Could someone please review this?
On 2019-09-04 03:15, Jethro Beekman wrote:
> Some flash controllers don't have a software sequencer. Avoid
> configuring the register addresses for it, and double check
> everywhere that its not accidentally trying to be used.
>
> Every use of `sregs` is now guarded by a check of `sregs` or
> `swseq_reg`. The check might be done in the calling function.
>
> Signed-off-by: Jethro Beekman <jethro@...tanix.com>
> ---
> drivers/mtd/spi-nor/intel-spi.c | 23 ++++++++++++++++-------
> 1 file changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
> index 1ccf23f..195cdca 100644
> --- a/drivers/mtd/spi-nor/intel-spi.c
> +++ b/drivers/mtd/spi-nor/intel-spi.c
> @@ -187,12 +187,16 @@ static void intel_spi_dump_regs(struct intel_spi *ispi)
> dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
> readl(ispi->pregs + PR(i)));
>
> - value = readl(ispi->sregs + SSFSTS_CTL);
> - dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
> - dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
> - readl(ispi->sregs + PREOP_OPTYPE));
> - dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
> - dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
> + if (ispi->sregs) {
> + value = readl(ispi->sregs + SSFSTS_CTL);
> + dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
> + dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
> + readl(ispi->sregs + PREOP_OPTYPE));
> + dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
> + readl(ispi->sregs + OPMENU0));
> + dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
> + readl(ispi->sregs + OPMENU1));
> + }
>
> if (ispi->info->type == INTEL_SPI_BYT)
> dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
> @@ -367,6 +371,11 @@ static int intel_spi_init(struct intel_spi *ispi)
> !(uvscc & ERASE_64K_OPCODE_MASK))
> ispi->erase_64k = false;
>
> + if (ispi->sregs == NULL && (ispi->swseq_reg || ispi->swseq_erase)) {
> + dev_err(ispi->dev, "software sequencer not supported, but required\n");
> + return -EINVAL;
> + }
> +
> /*
> * Some controllers can only do basic operations using hardware
> * sequencer. All other operations are supposed to be carried out
> @@ -383,7 +392,7 @@ static int intel_spi_init(struct intel_spi *ispi)
> val = readl(ispi->base + HSFSTS_CTL);
> ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
>
> - if (ispi->locked) {
> + if (ispi->locked && ispi->sregs) {
> /*
> * BIOS programs allowed opcodes and then locks down the
> * register. So read back what opcodes it decided to support.
>
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