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Date: Mon, 16 Sep 2019 06:41:17 -0700 From: kan.liang@...ux.intel.com To: peterz@...radead.org, acme@...nel.org, mingo@...hat.com, linux-kernel@...r.kernel.org Cc: tglx@...utronix.de, jolsa@...nel.org, eranian@...gle.com, alexander.shishkin@...ux.intel.com, ak@...ux.intel.com, Kan Liang <kan.liang@...ux.intel.com> Subject: [PATCH V4 03/14] perf/x86/intel: Move BTS index to 47 From: Kan Liang <kan.liang@...ux.intel.com> The bit 48 in the PERF_GLOBAL_STATUS is used to indicate the overflow status of PERF_METRICS counters now. Move BTS index to 47. Signed-off-by: Kan Liang <kan.liang@...ux.intel.com> --- New patch for V4 arch/x86/include/asm/perf_event.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 9f15a700d1db..eb460b63e07b 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -175,11 +175,11 @@ struct x86_pmu_capability { /* * We model BTS tracing as another fixed-mode PMC. * - * We choose a value in the middle of the fixed event range, since lower + * We choose value 47 for the fixed index of BTS, since lower * values are used by actual fixed events and higher values are used * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. */ -#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16) +#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15) #define GLOBAL_STATUS_COND_CHG BIT_ULL(63) #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62) -- 2.17.1
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