linux-kernel - Re: [PATCH v3 0/4] x86/mce: Add supports for Zhaoxin MCA

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Message-ID: <alpine.DEB.2.21.1909161539510.1887@nanos.tec.linutronix.de>
Date:   Mon, 16 Sep 2019 15:49:09 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Tony W Wang-oc <TonyWWang-oc@...oxin.com>
cc:     "tony.luck@...el.com" <tony.luck@...el.com>,
        "Borislav Petkov (bp@...en8.de)" <bp@...en8.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "yazen.ghannam@....com" <yazen.ghannam@....com>,
        "vishal.l.verma@...el.com" <vishal.l.verma@...el.com>,
        "qiuxu.zhuo@...el.com" <qiuxu.zhuo@...el.com>,
        David Wang <DavidWang@...oxin.com>,
        "Cooper Yan(BJ-RD)" <CooperYan@...oxin.com>,
        "Qiyuan Wang(BJ-RD)" <QiyuanWang@...oxin.com>,
        "Herry Yang(BJ-RD)" <HerryYang@...oxin.com>
Subject: Re: [PATCH v3 0/4] x86/mce: Add supports for Zhaoxin MCA

On Mon, 16 Sep 2019, Tony W Wang-oc wrote:

> Zhaoxin newer CPUs support MCE, CMCI and LMCE that compatible with
> Intel's "Machine-Check Architecture".

Thanks for providing a cover letter. Though threading does not work either
with that simply because the 1-4/4 mails lack a

   References: <Message-id-of-cover-letter>

tag. They have some weird:

   Thread-Index: AdVsgZ9UPwR7QKdtRlW4qXXe20fCvg==

tag, but that is different for every mail.

   Thread-Index: AdVsghaYSu2N9NgNSwS4zHAPRb3wjg==

'Thread-Index' is a MS Outlook specific header which is not supported by
real MUAs.

Please make sure to fix that when you are going to send the next round of
patches. Send them to yourself first and check the mail headers for a
proper References: tag chain. If you want to know how that looks just have
a look at the mail headers of any properly threaded patch series which you
received from LKML.

Thanks,

	tglx