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Message-Id: <1568793876-9009-3-git-send-email-gareth.williams.jx@renesas.com>
Date: Wed, 18 Sep 2019 09:04:34 +0100
From: Gareth Williams <gareth.williams.jx@...esas.com>
To: Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Cc: Gareth Williams <gareth.williams.jx@...esas.com>,
Phil Edworthy <phil.edworthy@...esas.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v2 2/4] dt-bindings: snps,dw-apb-ssi: Add optional clock domain information
Note in the bindings documentation that pclk should be renamed if a clock
domain is used to enable the optional bus clock.
Signed-off-by: Gareth Williams <gareth.williams.jx@...esas.com>
---
v2: Introduced this patch.
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index f54c8c3..3ed08ee 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -16,7 +16,8 @@ Required properties:
Optional properties:
- clock-names : Contains the names of the clocks:
"ssi_clk", for the core clock used to generate the external SPI clock.
- "pclk", the interface clock, required for register access.
+ "pclk", the interface clock, required for register access. If a clock domain
+ used to enable this clock then it should be named "pclk_clkdomain".
- cs-gpios : Specifies the gpio pins to be used for chipselects.
- num-cs : The number of chipselects. If omitted, this will default to 4.
- reg-io-width : The I/O register width (in bytes) implemented by this
--
2.7.4
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