linux-kernel - Re: [PATCH 3/3] reset: add support for the Meson-A1 SoC Reset Controller

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Date:   Wed, 18 Sep 2019 14:39:38 +0200
From:   Neil Armstrong <narmstrong@...libre.com>
To:     Xingyu Chen <xingyu.chen@...ogic.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Kevin Hilman <khilman@...libre.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Jerome Brunet <jbrunet@...libre.com>,
        Hanjie Lin <hanjie.lin@...ogic.com>,
        Jianxin Pan <jianxin.pan@...ogic.com>,
        linux-amlogic@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] reset: add support for the Meson-A1 SoC Reset
 Controller

On 18/09/2019 14:12, Xingyu Chen wrote:
> The number of RESET registers and offset of RESET_LEVEL register for
> Meson-A1 are different from previous SoCs, In order to describe these
> differences, we introduce the struct meson_reset_param.
> 
> Signed-off-by: Xingyu Chen <xingyu.chen@...ogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@...ogic.com>
> ---
>  drivers/reset/reset-meson.c | 35 ++++++++++++++++++++++++++++-------
>  1 file changed, 28 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
> index 5242e06..d9541c1 100644
> --- a/drivers/reset/reset-meson.c
> +++ b/drivers/reset/reset-meson.c
> @@ -64,12 +64,16 @@
>  #include <linux/types.h>
>  #include <linux/of_device.h>
>  
> -#define REG_COUNT	8
>  #define BITS_PER_REG	32
> -#define LEVEL_OFFSET	0x7c
> +
> +struct meson_reset_param {
> +	int reg_count;
> +	int level_offset;
> +};
>  
>  struct meson_reset {
>  	void __iomem *reg_base;
> +	const struct meson_reset_param *param;
>  	struct reset_controller_dev rcdev;
>  	spinlock_t lock;
>  };
> @@ -95,10 +99,12 @@ static int meson_reset_level(struct reset_controller_dev *rcdev,
>  		container_of(rcdev, struct meson_reset, rcdev);
>  	unsigned int bank = id / BITS_PER_REG;
>  	unsigned int offset = id % BITS_PER_REG;
> -	void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
> +	void __iomem *reg_addr;
>  	unsigned long flags;
>  	u32 reg;
>  
> +	reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
> +
>  	spin_lock_irqsave(&data->lock, flags);
>  
>  	reg = readl(reg_addr);
> @@ -130,10 +136,21 @@ static const struct reset_control_ops meson_reset_ops = {
>  	.deassert	= meson_reset_deassert,
>  };
>  
> +static const struct meson_reset_param meson8b_param = {
> +	.reg_count	= 8,
> +	.level_offset	= 0x7c,
> +};
> +
> +static const struct meson_reset_param meson_a1_param = {
> +	.reg_count	= 3,
> +	.level_offset	= 0x40,
> +};
> +
>  static const struct of_device_id meson_reset_dt_ids[] = {
> -	 { .compatible = "amlogic,meson8b-reset" },
> -	 { .compatible = "amlogic,meson-gxbb-reset" },
> -	 { .compatible = "amlogic,meson-axg-reset" },
> +	 { .compatible = "amlogic,meson8b-reset",    .data = &meson8b_param},
> +	 { .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
> +	 { .compatible = "amlogic,meson-axg-reset",  .data = &meson8b_param},
> +	 { .compatible = "amlogic,meson-a1-reset",   .data = &meson_a1_param},
>  	 { /* sentinel */ },
>  };
>  
> @@ -151,12 +168,16 @@ static int meson_reset_probe(struct platform_device *pdev)
>  	if (IS_ERR(data->reg_base))
>  		return PTR_ERR(data->reg_base);
>  
> +	data->param = of_device_get_match_data(&pdev->dev);
> +	if (!data->param)
> +		return -ENODEV;
> +
>  	platform_set_drvdata(pdev, data);
>  
>  	spin_lock_init(&data->lock);
>  
>  	data->rcdev.owner = THIS_MODULE;
> -	data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
> +	data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
>  	data->rcdev.ops = &meson_reset_ops;
>  	data->rcdev.of_node = pdev->dev.of_node;
>  
> 

Reviewed-by: Neil Armstrong <narmstrong@...libre.com>