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Message-ID: <9e705d2d22d040f4a170839466b38f5b@AcuMS.aculab.com>
Date: Thu, 19 Sep 2019 09:06:47 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Tim Chen' <tim.c.chen@...ux.intel.com>,
Parth Shah <parth@...ux.ibm.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Peter Zijlstra <peterz@...radead.org>,
Patrick Bellasi <patrick.bellasi@....com>,
"subhra mazumdar" <subhra.mazumdar@...cle.com>,
Valentin Schneider <valentin.schneider@....com>
CC: "mingo@...hat.com" <mingo@...hat.com>,
"morten.rasmussen@....com" <morten.rasmussen@....com>,
"dietmar.eggemann@....com" <dietmar.eggemann@....com>,
"pjt@...gle.com" <pjt@...gle.com>,
"vincent.guittot@...aro.org" <vincent.guittot@...aro.org>,
"quentin.perret@....com" <quentin.perret@....com>,
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"daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
"tj@...nel.org" <tj@...nel.org>,
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Subject: RE: Usecases for the per-task latency-nice attribute
From: Tim Chen
> Sent: 18 September 2019 18:16
...
> Some users are running machine learning batch tasks with AVX512, and have observed
> that these tasks affect the tasks needing a fast response. They have to
> rely on manual CPU affinity to separate these tasks. With appropriate
> latency hint on task, the scheduler can be taught to separate them.
Will (or can) the scheduler pre-empt a low priority process that is spinning
in userspace in order to allow a high priority (or low latency) process run
on that cpu?
My suspicion is that the process switch can't happen until (at least) the
next hardware interrupt - and possibly only a timer tick into the scheduler.
David
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