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Message-ID: <1568884242-22775-2-git-send-email-chunfeng.yun@mediatek.com>
Date: Thu, 19 Sep 2019 17:10:33 +0800
From: Chunfeng Yun <chunfeng.yun@...iatek.com>
To: Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh+dt@...nel.org>
CC: Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Chunfeng Yun <chunfeng.yun@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: [PATCH v3 02/11] dt-bindings: phy-mtk-tphy: make the ref clock optional
Make the ref clock optional, then we no need refer to a fixed-clock
in DTS anymore when the clock of USB3 PHY comes from oscillator
directly
Signed-off-by: Chunfeng Yun <chunfeng.yun@...iatek.com>
Acked-by: Rob Herring <robh@...nel.org>
---
v3: add acked-by Rob
v2: no changes
---
.../devicetree/bindings/phy/phy-mtk-tphy.txt | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
index ce6abfbdfbe1..1f4a36dd80e0 100644
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
@@ -34,12 +34,6 @@ Optional properties (controller (parent) node):
Required properties (port (child) node):
- reg : address and length of the register set for the port.
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock-names
-- clock-names : must contain
- "ref": 48M reference clock for HighSpeed analog phy; and 26M
- reference clock for SuperSpeed analog phy, sometimes is
- 24M, 25M or 27M, depended on platform.
- #phy-cells : should be 1 (See second example)
cell after port phandle is phy type from:
- PHY_TYPE_USB2
@@ -48,6 +42,13 @@ Required properties (port (child) node):
- PHY_TYPE_SATA
Optional properties (PHY_TYPE_USB2 port (child) node):
+- clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+- clock-names : may contain
+ "ref": 48M reference clock for HighSpeed anolog phy; and 26M
+ reference clock for SuperSpeed anolog phy, sometimes is
+ 24M, 25M or 27M, depended on platform.
+
- mediatek,eye-src : u32, the value of slew rate calibrate
- mediatek,eye-vrt : u32, the selection of VRT reference voltage
- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
--
2.23.0
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