linux-kernel - Missing 'assigned-clocks' in usdhc node of i.MX8MQ/MM/MN dtsi?

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Message-ID: <e6ce599e-597a-6f67-d5d1-5487f50c7d0d@kontron.de>
Date:   Thu, 19 Sep 2019 09:56:51 +0000
From:   Schrempf Frieder <frieder.schrempf@...tron.de>
To:     Anson Huang <Anson.Huang@....com>,
        Rob Herring <robh+dt@...nel.org>,
        "Mark Rutland" <mark.rutland@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        "leonard.crestez@....com" <leonard.crestez@....com>,
        "daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
        "ping.bai@....com" <ping.bai@....com>,
        "daniel.baluta@....com" <daniel.baluta@....com>,
        "jun.li@....com" <jun.li@....com>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "abel.vesa@....com" <abel.vesa@....com>,
        "andrew.smirnov@...il.com" <andrew.smirnov@...il.com>,
        "angus@...ea.ca" <angus@...ea.ca>,
        "ccaione@...libre.com" <ccaione@...libre.com>,
        "agx@...xcpu.org" <agx@...xcpu.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        NXP Linux Team <linux-imx@....com>
Subject: Missing 'assigned-clocks' in usdhc node of i.MX8MQ/MM/MN dtsi?

Hi,

I wonder why imx8mq.dtsi, imx8mm.dtsi and imx8mn.dtsi have 
'assigned-clocks' and 'assigned-clock-rates' set for all usdhc nodes, 
except for usdhc2.

Is this on purpose? Is it a flaw?

Thanks,
Frieder

Extract from imx8mm.dtsi:

usdhc1: mmc@...40000 {
	[...]
	assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	[...]
};

usdhc2: mmc@...50000 {
	compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
	reg = <0x30b50000 0x10000>;
	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk IMX8MM_CLK_DUMMY>,
		 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
		 <&clk IMX8MM_CLK_USDHC2_ROOT>;
	clock-names = "ipg", "ahb", "per";
	fsl,tuning-start-tap = <20>;
	fsl,tuning-step= <2>;
	bus-width = <4>;
	status = "disabled";
};

usdhc3: mmc@...60000 {
	[...]
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	[...]
};