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Message-ID: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com>
Date: Thu, 19 Sep 2019 08:11:01 -0400
From: Jianxin Pan <jianxin.pan@...ogic.com>
To: Kevin Hilman <khilman@...libre.com>,
<linux-amlogic@...ts.infradead.org>
CC: Jianxin Pan <jianxin.pan@...ogic.com>,
Rob Herring <robh+dt@...nel.org>,
Neil Armstrong <narmstrong@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
<linux-pm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, Jian Hu <jian.hu@...ogic.com>,
Hanjie Lin <hanjie.lin@...ogic.com>,
Victor Wan <victor.wan@...ogic.com>,
Xingyu Chen <xingyu.chen@...ogic.com>
Subject: [PATCH 0/3] arm64: meson: add support for A1 Power Domains
This patchset introduces a "Secure Power Doamin Controller". In A1/C1, power
controller registers such as PWRCTRL_FOCRSTN, PWRCTRL_PWR_OFF, PWRCTRL_MEM_PD
and PWRCTRL_ISO_EN, are in the secure domain, and should be accessed from ATF
by smc.
This patchset is based on A1 DTB series at [0].
[0] https://lore.kernel.org/linux-amlogic/1568276370-54181-1-git-send-email-jianxin.pan@amlogic.com
Jianxin Pan (3):
dt-bindings: power: add Amlogic secure power domains bindings
soc: amlogic: Add support for Secure power domains controller
arm64: dts: meson: a1: add secure power domain controller
.../bindings/power/amlogic,meson-sec-pwrc.yaml | 32 ++++
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 +
drivers/soc/amlogic/Kconfig | 13 ++
drivers/soc/amlogic/Makefile | 1 +
drivers/soc/amlogic/meson-secure-pwrc.c | 182 +++++++++++++++++++++
include/dt-bindings/power/meson-a1-power.h | 32 ++++
6 files changed, 266 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
create mode 100644 include/dt-bindings/power/meson-a1-power.h
--
2.7.4
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